Special Issue: Engineering applications of representations of function, Part 1

In engineering design, the end goal is the creation of an artifact, product, system, or process that fulfills some functional requirements at some desired level of performance. As such, knowledge of functionality is essential in a wide variety of tasks in engineering activities, including modeling, generation, modification, visualization, explanation, evaluation, diagnosis, and repair of these artifacts and processes. A formal representation of functionality is essential for supporting any of these activities on computers. The goal of Parts 1 and 2 of this Special Issue is to bring together the state of knowledge of representing functionality in engineering applications from both the engineering and the artificial intelligence (AI) research communities.

Photo-Defined Electrically Assisted Etching Method for Metal Stencil Fabrication

Metal stencils are well known in electronics printing application such as for dispensing solder paste for surface mounting, printing embedded passive elements in multilayer structures, etc. For microprinting applications using stencils, the print quality depends on the smoothness of the stencil aperture and its dimensional accuracy, which in turn are invariably related to the method used to manufacture the stencils. In this paper, fabrication of metal stencils using a photo-defined electrically assisted etching method is described. Apertures in the stencil were made in neutral electrolyte using three different types of impressed current, namely, dc, pulsed dc, and periodic pulse reverse (PPR). Dimensional accuracy and wall smoothness of the etched apertures in each of the current waveforms were compared. Finally, paste transfer efficiency of the stencil obtained using PPR was calculated and compared with those of a laser-cut electropolished stencil. It is observed that the stencil fabricated using current in PPR waveform has better dimensional accuracy and aperture wall smoothness than those obtained with dc and pulsed dc. From the paste transfer efficiency experiment, it is concluded that photo-defined electrically assisted etching method can provide an alternate route for fabrication of metal stencils for future microelectronics printing applications.

Two new families of low-correlation interleaved QAM sequence

Two families of low correlation QAM sequences are presented here. In a CDMA setting, these sequences have the ability to transport a large amount of data as well as enable variable-rate signaling on the reverse link. The first family Á2SQ - B2− is constructed by interleaving 2 selected QAM sequences. This family is defined over M 2-QAM, where M = 2 m , m ≥ 2. Over 16-QAM, the normalized maximum correlation [`(q)]maxmax is bounded above by <~1.17 ÖNUnknown control sequence '\lesssim' , where N is the period of the sequences in the family. This upper bound on [`(q)]maxmax is the lowest among all known sequence families over 16-QAM.The second family Á4SQ4 is constructed by interleaving 4 selected QAM sequences. This family is defined over M 2-QAM, where M = 2 m , m ≥ 3, i.e., 64-QAM and beyond. The [`(q)]maxmax for sequences in this family over 64-QAM is upper bounded by <~1.60 ÖNUnknown control sequence '\lesssim' . For large M, [`(q)]max <~1.64 ÖNUnknown control sequence '\lesssim' . These upper bounds on [`(q)]maxmax are the lowest among all known sequence families over M 2-QAM, M = 2 m , m ≥ 3.

Low correlation interleaved QAM sequences

A low correlation interleaved QAM sequence family is presented here. In a CDMA setting, these sequences have the ability to transport a large amount of data as well as enable variable-rate signaling on the reverse link. The new interleaved selected family INQ has period N, normalized maximum correlation parameter thetasmacrmax bounded above by lsim a radicN, where a ranges from 1.17 in the 16-QAM case to 1.99 for large M2-QAM, where M = 2m, m ges 2. Each user is enabled to transfer m + 1 bits of data per period of the spreading sequence. These constructions have the lowest known value of maximum correlation of any sequence family with the same alphabet.

Network Coding for TCP Throughput Enhancement over a Multi-Hop wireless Network

The poor performance of TCP over multi-hop wireless networks is well known. In this paper we explore to what extent network coding can help to improve the throughput performance of TCP controlled bulk transfers over a chain topology multi-hop wireless network. The nodes use a CSMA/ CA mechanism, such as IEEE 802.11’s DCF, to perform distributed packet scheduling. The reverse flowing TCP ACKs are sought to be X-ORed with forward flowing TCP data packets. We find that, without any modification to theMAC protocol, the gain from network coding is negligible. The inherent coordination problem of carrier sensing based random access in multi-hop wireless networks dominates the performance. We provide a theoretical analysis that yields a throughput bound with network coding. We then propose a distributed modification of the IEEE 802.11 DCF, based on tuning the back-off mechanism using a feedback approach. Simulation studies show that the proposed mechanism when combined with network coding, improves the performance of a TCP session by more than 100%.

Variational Asymptotic Analysis of a Self-healing SMA Composite

A Shape Memory Alloy (SMA) wire reinforced composite shell structure is analyzed for self-healing characteristic using Variational Asymptotic Method (VAM). SMA behavior is modeled using a onedimensional constitutive model. A pre-notched specimen is loaded longitudinally to simulate crack propagation. The loading process is accompanied by martensitic phase transformation in pre-strained SMA wires, bridging the crack. To heal the composite, uniform heating is required to initiate reverse transformation in the wires and bringing the crack faces back into contact. The pre-strain in the SMA wires used for reinforcement, causes a closure force across the crack during reverse transformation of the wires under heating. The simulation can be useful in design of self-healing composite structures using SMA. Effect of various parameters, like composite and SMA material properties and the geometry of the specimen, on the cracking and self-healing can also be studied.

A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications

The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.

Effect of strain path change on the evolution of texture and microstructure during rolling of copper and nickel

The effect of strain path change during rolling has been investigated for copper and nickel using X-ray diffraction and electron back scatter diffraction as well as crystal plasticity simulations. Four different strain paths namely: (i) unidirectional rolling; (ii) reverse rolling; (iii) two-step cross rolling and (iv) multi-step cross rolling were employed to decipher the effect of strain path change on the evolution of deformation texture and microstructure. The cross rolled samples showed weaker texture with a prominent Bs {1 1 0}< 1 1 2 > and P(B(ND)) {1 1 0}< 1 1 1 > component in contrast to the unidirectional and reverse rolled samples where strong S {1 2 3}< 6 3 4 > and Cu {1 1 2}< 1 1 1 > components were formed. This was more pronounced for copper samples compared to nickel. The cross rolled samples were characterized by lower anisotropy and Taylor factor as well as less variation in Lankford parameter. Viscoplastic self-consistent simulations indicated that slip activity on higher number of octahedral slip systems can explain the weaker texture as well as reduced anisotropy in the cross rolled samples. (C) 2011 Elsevier B.V. All rights reserved.

An Empirical Study of Synthesis of Multiple State Devices by Engineering Designers

Automated synthesis of mechanical designs is an important step towards the development of an intelligent CAD system. Research into methods for supporting conceptual design using automated synthesis has attracted much attention in the past decades. The research work presented here is based on an empirical study of the process of synthesis of multiple state mechanical devices. As a background to the work, the paper explores concepts of what mechanical device, state, single state and multiple state are, and in the context of the above observational studies, attempts to identify the outstanding issues for supporting multiple state synthesis of mechanical devices.

Recent Advances in Low CTE and High Density System-on-a-Package (SOP) Substrate with Thin Film Component Integration

The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, optical, and sensor functions integrated in a single package/module. The goal of this effort is to develop a platform substrate technology providing very high wiring density and embedded thin film passive and active components using PWB compatible materials and processes. The latest SOP baseline process test vehicle has been fabricated on novel Si-matched CTE, high modulus C-SiC composite core substrates using 10mum thick BCB dielectric films with loss tangent of 0.0008 and dielectric constant of 2.65. A semi-additive plating process has been developed for multilayer microvia build-up using BCB without the use of any vacuum deposition or polishing/CMP processes. PWB and package substrate compatible processes such as plasma surface treatment/desmear and electroless/electrolytic pulse reverse plating was used. The smallest line width and space demonstrated in this paper is 6mum with microvia diameters in the 15-30mum range. This build-up process has also been developed on medium CTE organic laminates including MCL-E-679F from Hitachi Chemical and PTFE laminates with Cu-Invar-Cu core. Embedded decoupling capacitors with capacitance density of >500nF/cm2 have been integrated into the build-up layers using sol-gel synthesized BaTiO3 thin films (200-300nm film thickness) deposited on copper foils and integrated using vacuum lamination and subtractive etch processes. Thin metal alloy resistor films have been integrated into the SOP substrate using two methods: (a) NiCrAlSi thin films (25ohms per square) deposited on copper foils (Gould Electronics) laminated on the build-up layers and two step etch process for resistor definition, and (b) electroless plated Ni-W-P thin films (70 ohms to few Kohms per square) on the BCB dielectric by plasma surface treatment and activation. The electrical design and build-up layer structure along- - with key materials and processes used in the fabrication of the SOP4 test vehicle were presented in this paper. Initial results from the high density wiring and embedded thin film components were also presented. The focus of this paper is on integration of materials, processes and structures in a single package substrate for system-on-a-package (SOP) implementation