(Table 1) Reproductive performance of brown skua pairs with and without feeding territories at Potter Peninsula/King George Island from 1998/1999 to 2000/2001

In the maritime Antarctic, brown skuas (Catharacta antarctica lonnbergi) show two foraging strategies: some pairs occupy feeding territories in penguin colonies, while others can only feed in unoccupied areas of a penguin colony without defending a feeding territory. One-third of the studied breeding skua population in the South Shetlands occupied territories of varying size (48 to >3,000 penguin nests) and monopolised 93% of all penguin nests in sub-colonies. Skuas without feeding territories foraged in only 7% of penguin sub-colonies and in part of the main colony. Females owning feeding territories were larger in body size than females without feeding territories; no differences in size were found in males. Territory holders permanently controlled their resources but defence power diminished towards the end of the reproductive season. Territory ownership guaranteed sufficient food supply and led to a 5.5 days earlier egg-laying and chick-hatching. Short distances between nest and foraging site allowed territorial pairs a higher nest-attendance rate such that their chicks survived better (71%) than chicks from skua pairs without feeding territories (45%). Due to lower hatching success in territorial pairs, no difference in breeding success of pairs with and without feeding territories was found in 3 years. We conclude that skuas owning feeding territories in penguin colonies benefit from the predictable and stable food resource by an earlier termination of the annual breeding cycle and higher offspring survivorship.

Microcharcoal concentration and elongation, and age model of sediment core MD96-2098

Although grassland and savanna occupy only a quarter of the world's vegetation, burning in these ecosystems accounts for roughly half the global carbon emissions from fire. However, the processes that govern changes in grassland burning are poorly understood, particularly on time scales beyond satellite records. We analyzed microcharcoal, sediments, and geochemistry in a high-resolution marine sediment core off Namibia to identify the processes that have controlled biomass burning in southern African grassland ecosystems under large, multimillennial-scale climate changes. Six fire cycles occurred during the past 170,000 y in southern Africa that correspond both in timing and magnitude to the precessional forcing of north-south shifts in the Intertropical Convergence Zone. Contrary to the conventional expectation that fire increases with higher temperatures and increased drought, we found that wetter and cooler climates cause increased burning in the study region, owing to a shift in rainfall amount and seasonality (and thus vegetation flammability). We also show that charcoal morphology (i.e., the particle's length-to-width ratio) can be used to reconstruct changes in fire activity as well as biome shifts over time. Our results provide essential context for understanding current and future grassland-fire dynamics and their associated carbon emissions.

Food composition of beryx-alfonsino over submarine rises near Azores

Qualitative and quantitative food composition, as well as intensity of feeding of beryx-alfonsino Beryx splendens was examined on banks near the Azores. Data are presented with respect to size groups and taking into account type of feeding of males and females. Crustaceans and fishes were constituents of their feeding ration. A tendency toward increase in the number of consumed fishes in the course of ontogenetic development of beryx-alfonsino was noted. Beryx-alfonsino was shown to occupy the trophic level of consumers of the third order performing function of a deep-water predator.

Sedimentology and gas hydrates of IODP Expedition 311 samples

Expedition 311 of the Integrated Ocean Drilling Program (IODP) to northern Cascadia recovered gas-hydrate bearing sediments along a SW-NE transect from the first ridge of the accretionary margin to the eastward limit of gas-hydrate stability. In this study we contrast the gas gas-hydrate distribution from two sites drilled ~ 8 km apart in different tectonic settings. At Site U1325, drilled on a depositional basin with nearly horizontal sedimentary sequences, the gas-hydrate distribution shows a trend of increasing saturation toward the base of gas-hydrate stability, consistent with several model simulations in the literature. Site U1326 was drilled on an uplifted ridge characterized by faulting, which has likely experienced some mass wasting events. Here the gas hydrate does not show a clear depth-distribution trend, the highest gas-hydrate saturation occurs well within the gas-hydrate stability zone at the shallow depth of ~ 49 mbsf. Sediments at both sites are characterized by abundant coarse-grained (sand) layers up to 23 cm in thickness, and are interspaced within fine-grained (clay and silty clay) detrital sediments. The gas-hydrate distribution is punctuated by localized depth intervals of high gas-hydrate saturation, which preferentially occur in the coarse-grained horizons and occupy up to 60% of the pore space at Site U1325 and > 80% at Site U1326. Detailed analyses of contiguous samples of different lithologies show that when enough methane is present, about 90% of the variance in gas-hydrate saturation can be explained by the sand (> 63 µm) content of the sediments. The variability in gas-hydrate occupancy of sandy horizons at Site U1326 reflects an insufficient methane supply to the sediment section between 190 and 245 mbsf.

Abundance patterns and isotopic signals of morphotypes of Globigerinoides ruber

The chemical composition of shells of the planktonic foraminifer Globigerinoides ruber (white) is frequently used to determine past sea surface conditions. Recently, it has been shown that arbitrarily defined morphotypes within this species exhibit different chemical and isotopic signatures. Here, we investigate the occurrence through time and in space of morphological types of G. ruber (white) in late Quaternary and Holocene sediments of the central and the eastern Mediterranean Sea. In 115 samples representing two distinct time intervals (MIS 1-2 and MIS 9-12) at ODP Site 964 and the piston core GeoTü-SL96, we have defined three morphological types within this species and determined their relative abundances and stable isotopic composition. A quantitative analysis of morphological variation within G. ruber (white) in four samples revealed that the subjectively defined morphotypes occupy separate segments of a continuous and homogenous morphospace. We further show that the abundance of the morphotypes changes significantly between glacials and interglacials and that the three morphotypes of G. ruber show significant offsets in their stable isotopic composition. These offsets are consistent within glacial and interglacial stages but their sign is systematically reversed between the two Sites. Since the isotopic shifts among the three G. ruber morphotypes are systematic and often exceed 1per mil, their understanding is essential for the interpretation of all G. ruber-based proxy records for the paleoceanographic development of the Mediterranean during the late Quaternary.

Potential connections (least-cost paths) between existing and potential bison habitat patches in the Carpathian Mountains

Habitat connectivity is important for the survival of species that occupy habitat patches too small to sustain an isolated population. A prominent example of such a species is the European bison (Bison bonasus), occurring only in small, isolated herds, and whose survival will depend on establishing larger, well-connected populations. Our goal here was to assess habitat connectivity of European bison in the Carpathians. We used an existing bison habitat suitability map and data on dispersal barriers to derive cost surfaces, representing the ability of bison to move across the landscape, and to delineate potential connections (as least-cost paths) between currently occupied and potential habitat patches. Graph theory tools were then employed to evaluate the connectivity of all potential habitat patches and their relative importance in the network. Our analysis showed that existing bison herds in Ukraine are isolated. However, we identified several groups of well-connected habitat patches in the Carpathians which could host a large population of European bison. Our analysis also located important dispersal corridors connecting existing herds, and several promising locations for future reintroductions (especially in the Eastern Carpathians) that should have a high priority for conservation efforts. In general, our approach indicates the most important elements within a landscape mosaic for providing and maintaining the overall connectivity of different habitat networks and thus offers a robust and powerful tool for conservation planning.

Geochemistry and isotopic ratios of boninites and related rocks of the Izu-Bonin Forearc

Twenty-six samples representing the wide range of lithologies (low- and intermediate-Ca boninites and bronzite andesites, high-Ca boninites, basaltic andesites-rhyolites) drilled during Leg 125 at Sites 782 and 786 on the Izu-Bonin outer-arc high have been analyzed for Sr, Nd, and Pb isotopes. Nd-Sr isotope covariations show that most samples follow a trend parallel to a line from Pacific MORB mantle (PMM) to Pacific Volcanogenic sediment (PVS) but displaced slightly toward more radiogenic Sr. Pb isotope covariations show that all the Eocene-Oligocene samples plot along the Northern Hemisphere Reference Line, indicating little or no Pb derived from subducted pelagic sediment in their source. Two young basaltic andesite clasts within sediment do have a pelagic sediment signature but this may have been gained by alteration rather than subduction. In all isotopic projections, the samples form consistent groupings: the tholeiites from Site 782 and Hole 786A plot closest to PMM, the boninites and related rocks from Sites 786B plot closest to PVS, and the boninite lavas from Hole 786A and late boninitic dikes from Hole 786B occupy an intermediate position. Isotope-trace element covariations indicate that these isotopic variations can be explained by a three-component mixing model. One component (A) has the isotopic signature of PMM but is depleted in the more incompatible elements. It is interpreted as representing suboceanic mantle lithosphere. A second component (B) is relatively radiogenic (epsilon-Nd = ca 4-6; 206Pb/204Pb = ca 19.0-19.3; epsilon-Sr = ca -10 to -6)). Its trace element pattern has, among other characteristics, a high Zr/Sm ratio, which distinguishes it from the ìnormalî fluid components associated with subduction and hotspot activity. There are insufficient data at present to tie down its origin: probably it was either derived from subducted lithosphere or volcanogenic sediment fused in amphibolite facies; or it represents an asthenospheric melt component that has been fractionated by interaction with amphibole-bearing mantle. The third component (C) is characterized by high contents of Sr and high epsilon-Sr values and is interpreted as a subducted fluid component. The mixing line on a diagram of Zr/Sr against epsilon-Sr suggests that component C may have enriched the lithosphere (component A) before component B. These components may also be present on a regional basis but, if so, may not have had uniform compositions. Only the boninitic series from nearby Chichijima would require an additional, pelagic sediment component. In general, these results are consistent with models of subduction of ridges and young lithosphere during the change from a ridge-transform to subduction geometry at the initiation of subduction in the Western Pacific.

Archive of the PASATA (PASsive Acoustic Tracking of Antarctic marine mammals) field documentation

Recordings from the PerenniAL Acoustic Observatory in the Antarctic ocean (PALAOA) show seasonal acoustic presence of 4 Antarctic ice-breeding seal species (Ross seal, Ommatophoca rossii, Weddell seal, Leptonychotes weddellii, crabeater, Lobodon carcinophaga, and leopard seal, Hydrurga leptonyx). Apart from Weddell seals, inhabiting the fast-ice in Atka Bay, the other three (pack-ice) species however have to date never (Ross and leopard seal) or only very rarely (crabeater seals) been sighted in the Atka Bay region. The aim of the PASATA project is twofold: the large passive acoustic hydrophone array (hereafter referred to as large array) aims to localize calling pack-ice pinniped species to obtain information on their location and hence the ice habitat they occupy. This large array consists of four autonomous passive acoustic recorders with a hydrophone sensor deployed through a drilled hole in the sea ice. The PASATA recordings are time-stamped and can therefore be coupled to the PALAOA recordings so that the hydrophone array spans the bay almost entirely from east to west. The second, smaller hydrophone array (hereafter referred to as small array), also consists of four autonomous passive acoustic recorders with hydrophone sensors deployed through drilled holes in the sea ice. The smaller array was deployed within a Weddell seal breeding colony, located further south in the bay, just off the ice shelf. Male Weddell seals are thought to defend underwater territories around or near tide cracks and breathing holes used by females. Vocal activity increases strongly during the breeding season and vocalizations are thought to be used underwater by males for the purpose of territorial defense and advertisement. With the smaller hydrophone array we aim to investigate underwater behaviour of vocalizing male and female Weddell seals to provide further information on underwater movement patterns in relation to the location of tide cracks and breathing holes. As a pilot project, one on-ice and three underwater camera systems have been deployed near breathing holes to obtain additional visual information on Weddell seal behavioural activity. Upon each visit in the breeding colony, a census of colony composition on the ice (number of animals, sex, presence of dependent pups, presence and severity of injuries-indicative of competition intensity) as well as GPS readings of breathing holes and positions of hauled out Weddell seals are taken.

‘This square is our home!’: the organisation of urban space in the spanish 15M movement

Why should a progressive planner/urbanist pay attention to the Spanish 15M movement? From a disciplinary standpoint, its most complex and interesting aspect, which could hypothetically be transferred to other contexts (as in fact happened in the Occupy Wall Street and Occupy London movements), is its 'spatiality'. This article analyses the spatial practices of the so called #spanishrevolution, one of the 2011 social movements that showed the possibility for a new collective appropriation and self-management (autogestion) of urban public space. Although the political goals of the movement were vague at the time of its inception, the practices and spatial imaginaries deployed by it have become consolidated and proven to be yet another of its more successful facets in promoting the spreading and organisation of the protest, making it a phenomenon that calls for reflection on the part of urban thinkers and planners.

Interstitial Ti for intermediate band formation in Ti-supersaturated silicon

We have analyzed by means of Rutherford backscattering spectrometry (RBS) the Ti lattice location and the degree of crystalline lattice recovery in heavily Ti implanted silicon layers subsequently pulsed laser melted (PLM). Theoretical studies have predicted that Ti should occupy interstitial sites in silicon for a metallic-intermediate band (IB) formation. The analysis of Ti lattice location after PLM processes is a crucial point to evaluate the IB formation that can be clarifyied by means of RBS measurements. After PLM, time-of-flight secondary ion mass spectrometry measurements show that the Ti concentration in the layers is well above the theoretical limit for IB formation. RBS measurements have shown a significant improvement of the lattice quality at the highest PLM energy density studied. The RBS channeling spectra reveals clearly that after PLM processes Ti impurities are mostly occupying interstitial lattice sites.

Mixing effect on volume growth of Fagus sylvatica and Pinus sylvestris is modulated by stand density

Despite the increasing relevance of mixed stands due to their potential benefits; little information is available with regard to the effect of mixtures on yield in forest systems. Hence, it is necessary to study inter-specific relationships, and the resulting yield in mixed stands, which may vary with stand development, site or stand density, etc. In Spain, the province of Navarra is considered one of the biodiversity reservoirs; however, mixed forests occupy only a small area, probably as a consequence of management plans, in which there is an excessive focus on the productivity aspect, favoring the presence of pure stands of the most marketable species. The aim of this paper is to study how growth efficiencies of beech (Fagus sylvatica) and pine (Pinus sylvestris) are modified by the admixture of the other species and to determine whether stand density modifies interspecific relationships and to what extent. Two models were fitted from Spanish National Forest Inventory data, for P. sylvestris and F. sylvatica respectively, which relate the growth efficiency of the species, i.e. the volume increment of the species divided by the species proportion by area, with dominant height, quadratic mean diameter, stocking degree, and the species proportions by area of each species. Growth efficiency of pine increased with the admixture of beech, decreasing this positive effect when stocking degree increased. However, the positive effect of pine admixture on beech growth was greater at higher stocking degrees. Growth efficiency of beech was also dependent on stand dominant height, resulting in a net negative mixing effect when stand dominant heights and stocking degrees were simultaneously low. There is a relatively large range of species proportions and stocking degrees which results in transgressive overyielding: higher volume increments in mixed stands than that of the most productive pure pine stands. We concluded that stocking degree is a key factor in between-species interactions, being the effects of mixing not always greater at higher stand densities, but it depends on species composition.

Ecualización y optimización de la codificación para la simulación de sistemas OFDM

Los sistemas basados en la técnica OFDM (Multiplexación por División de Frecuencias Ortogonales) son una evolución de los tradicionales sistemas FDM (Multiplexación por División de Frecuencia), gracias a la cual se consigue un mejor aprovechamiento del ancho de banda. En la actualidad los sistemas OFDM y sus variantes ocupan un lugar muy importante en las comunicaciones, estando implementados en diversos estándares como pueden ser: DVB-T (estándar de la TDT), ADSL, LTE, WIMAX, DAB (radio digital), etc. Debido a ello, en este proyecto se implementa un sistema OFDM en el que poder realizar diversas simulaciones para entender mejor su funcionamiento. Para ello nos vamos a valer de la herramienta Matlab. Los objetivos fundamentales dentro de la simulación del sistema es poner a prueba el empleo de turbo códigos (comparándolo con los códigos convolucionales tradicionales) y de un ecualizador. Todo ello con la intención de mejorar la calidad de nuestro sistema (recibir menos bits erróneos) en condiciones cada vez más adversas: relaciones señal a ruido bajas y multitrayectos. Para ello se han implementado las funciones necesarias en Matlab, así como una interfaz gráfica para que sea más sencillo de utilizar el programa y más didáctico. En los capítulos segundo y tercero de este proyecto se efectúa un estudio de las bases de los sistemas OFDM. En el segundo nos centramos más en un estudio teórico puro para después pasar en el tercero a centrarnos únicamente en la teoría de los bloques implementados en el sistema OFDM que se desarrolla en este proyecto. En el capítulo cuarto se explican las distintas opciones que se pueden llevar a cabo mediante la interfaz implementada, a la vez que se elabora un manual para el correcto uso de la misma. El quinto capítulo se divide en dos partes, en la primera se muestran las representaciones que puede realizar el programa, y en la segunda únicamente se realizan simulaciones para comprobar que tal responde nuestra sistema a distintas configuraciones de canal, y las a distintas configuraciones que hagamos nosotros de nuestro sistema (utilicemos una codificación u otra, utilicemos el ecualizador o el prefijo cíclico, etc…). Para finalizar, en el último capítulo se exponen las conclusiones obtenidas en este proyecto, así como posibles líneas de trabajo que seguir en próximas versiones del mismo. ABSTRACT. Systems based on OFDM (Orthogonal Frequency Division Multiplexing) technique are an evolution of traditional FDM (Frequency Division Multiplexing). Due to the use of OFDM systems are achieved by more efficient use of bandwidth. Nowadays, OFDM systems and variants of OFDM systems occupy a very important place in the world of communications, being implemented in standards such as DVB-T, ADSL, LTE, WiMAX, DAB (digital radio) and another more. For all these reasons, this project implements a OFDM system for performing various simulations for better understanding of OFDM system operation. The system has been simulated using Matlab. With system simulation we search to get two key objectives: to test the use of turbo codes (compared to traditional convolutional codes) and an equalizer. We do so with the intention of improving the quality of our system (receive fewer rates of bit error) in increasingly adverse conditions: lower signal-to-noise and multipath. For these reasons necessaries Matlab´s functions have been developed, and a GUI (User Graphical Interface) has been integrated so the program can be used in a easier and more didactic way. This project is divided into five chapters. In the second and third chapter of this project are developed the basis of OFDM systems. Being developed in the second one a pure theoretical study, while focusing only on block theory implemented in the OFDM system in the third one. The fourth chapter describes the options that can be carried out by the interface implemented. Furthermore the chapter is developed for the correct use of the interface. The fifth chapter is divided into two parts, the first part shows to us the representations that the program can perform, and the second one just makes simulations to check that our system responds to differents channel configurations (use of convolutional codes or turbo codes, the use of equalizer or cyclic prefix…). Finally, the last chapter presents the conclusions of this project and possible lines of work to follow in future versions.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

Herramienta de apoyo a la docencia en sistemas operativos

El proyecto fin de carrera de herramienta de apoyo a la docencia en Sistemas Operativos quiere ayudar al alumno a entender el funcionamiento de un planificador a corto plazo. Lo hace mediante una representación gráfica de procesos que ocupan o el procesador o distintas unidades de entrada/salida mientras transcurre el tiempo. El tiempo está dividido en ciclos de reloj de un procesador, a lo que a continuación se referirá como unidades de tiempo. Los procesos están definidos por su nombre, la instante de entrada que entran al sistema, su prioridad y la secuencia de unidades de tiempo en el procesador y unidades de entrada/salida que necesitan para terminar su trabajo. El alumno puede configurar el sistema a su gusto en cuanto al número y comportamiento de las unidades de entrada/salida. Puede definir que una unidad solo permita acceso exclusivo a los procesos, es decir que solo un proceso puede ocuparla simultáneamente, o que permita el acceso múltiple a sus recursos. El alumno puede construir un planificador a corto plazo propio, integrarlo en el sistema y ver cómo se comporta. Se debe usar la interfaz Java proporcionada para su construcción. La aplicación muestra datos estadísticos como por ejemplo la eficiencia del sistema (el tiempo activo de la CPU dividido por el tiempo total de la simulación), tiempos de espera de los procesos, etc. Se calcula después de cada unidad de tiempo para que el alumno pueda ver el momento exacto donde la simulación tomó un giro inesperado. La aplicación está compuesta por un motor de simulación que contiene toda la lógica y un conjunto de clases que forman la interfaz gráfica que se presenta al usuario. Estos dos componentes pueden ser reemplazados siempre y cuando se mantenga la definición de sus conectores igual. La aplicación la he hecho de manejo muy simple e interfaz fácil de comprender para que el alumno pueda dedicar todo su tiempo a probar distintas configuraciones y situaciones y así entender mejor la asignatura. ABSTRACT. The project is called “Tool to Support Teaching of the Subject Operating Systems” and is an application that aims to help students understand on a deeper level the inner workings of how an operating system handles multiple processes in need of CPU time by the means of a short-term planning algorithm. It does so with a graphical representation of the processes that occupy the CPU and different input/output devices as time passes by. Time is divided in CPU cycles, from now on referred to as time units. The processes are defined by their name, the moment they enter the system, their priority and the sequence of time units they need to finish their job. The student can configure the system by changing the number and behavior of the input/output devices. He or she can define whether a device should only allow exclusive access, i.e. only one process can occupy it at any given time, or if it should allow multiple processes to access its resources. The student can build a planning algorithm of his or her own and easily integrate it into the system to see how it behaves. The provided Java interface and the programming language Java should be used to build it. The application shows statistical data, e.g. the efficiency of the system (active CPU time divided by total simulation time) and time spent by the processes waiting in queues. The data are calculated after passing each time unit in order for the student to see the exact moment where the simulation took an unexpected turn. The application is comprised of a simulation motor, which handles all the logic, and a set of classes, which is the graphical user interface. These two parts can be replaced individually if the definition of the connecting interfaces stays the same. I have made the application to be very easy to use and with an easy to understand user interface so the student can spend all of his or her time trying out different configurations and scenarios in order to understand the subject better.

Modeling the shape hierarchy for visually guided grasping

The monkey anterior intraparietal area (AIP) encodes visual information about three-dimensional object shape that is used to shape the hand for grasping. We modeled shape tuning in visual AIP neurons and its relationship with curvature and gradient information from the caudal intraparietal area (CIP). The main goal was to gain insight into the kinds of shape parameterizations that can account for AIP tuning and that are consistent with both the inputs to AIP and the role of AIP in grasping. We first experimented with superquadric shape parameters. We considered superquadrics because they occupy a role in robotics that is similar to AIP , in that superquadric fits are derived from visual input and used for grasp planning. We also experimented with an alternative shape parameterization that was based on an Isomap dimension reduction of spatial derivatives of depth (i.e., distance from the observer to the object surface). We considered an Isomap-based model because its parameters lacked discontinuities between similar shapes. When we matched the dimension of the Isomap to the number of superquadric parameters, the superquadric model fit the AIP data somewhat more closely. However, higher-dimensional Isomaps provided excellent fits. Also, we found that the Isomap parameters could be approximated much more accurately than superquadric parameters by feedforward neural networks with CIP-like inputs. We conclude that Isomaps, or perhaps alternative dimension reductions of visual inputs to AIP, provide a promising model of AIP electrophysiology data. Further work is needed to test whether such shape parameterizations actually provide an effective basis for grasp control.