882 resultados para Low-Power Inverters
Resumo:
In this thesis various schemes using custom power devices for power quality improvement in low voltage distribution network are studied. Customer operated distributed generators makes a typical network non-radial and affect the power quality. A scheme considering different algorithm of DSTATCOM is proposed for power circulation and islanded operation of the system. To compensate reactive power overflow and facilitate unity power factor, a UPQC is introduced. Stochastic analysis is carried out for different scenarios to get a comprehensive idea about a real life distribution network. Combined operation of static compensator and voltage regulator is tested for the optimum quality and stability of the system.
Resumo:
为研究风电并网对互联系统低频振荡的影响,基于完整的双馈风电机组模型,定性分析了两区域互联系统在风电机组并网前后阻尼特性的变化情况.从双馈风电机组并网输送距离、并网容量、互联系统联络线传送功率、是否加装电力系统稳定器等多个方面,多角度分析了风电场并网对互联系统小干扰稳定及低频振荡特性的影响.之后,以两个包括两个区域的电力系统为例,进行了系统的计算分析和比较.结果表明,有双馈风电机组接入的互联电力系统,在不同运行模式下,双馈风电机组的并网输送距离、出力水平、联络线传送功率对低频振荡模式的影响在趋势和程度上均有显著差异,这样在对风电场进行入网规划、设计和运行时就需要综合考虑这些因素的影响.
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This paper proposes a multilevel inverter configuration which produces a hexagonal voltage space vector structure in the lower modulation region and a 12-sided polygonal space vector structure in the overmodulation region. A conventional multilevel inverter produces 6n plusmn 1 (n = odd) harmonics in the phase voltage during overmodulation and in the extreme square-wave mode of operation. However, this inverter produces a 12-sided polygonal space vector location, leading to the elimination of 6n plusmn 1 (n = odd) harmonics in the overmodulation region extending to a final 12-step mode of operation with a smooth transition. The benefits of this arrangement are lower losses and reduced torque pulsation in an induction motor drive fed from this converter at higher modulation indexes. The inverter is fabricated by using three conventional cascaded two-level inverters with asymmetric dc-bus voltages. A comparative simulation study of the harmonic distortion in the phase voltage and associated losses in conventional multilevel inverters and that of the proposed inverter is presented in this paper. Experimental validation on a prototype shows that the proposed converter is suitable for high-power applications because of low harmonic distortion and low losses.
Resumo:
The dynamics of reactions with low internal barriers are studied both analytically and numerically for two different models. Exact expressions for the average rate,kI, are obtained by solving the associated first passage time problems. Both the average rate constant, kI, and the numerically calculated long-time rate constant, kL, show a fractional power law dependence on the barrier height for very low barriers. The crossover of the reaction dynamics from low to high barrier is investigated.
Resumo:
The present trend in the industry is towards the use of power transistors in the development of efficient Pulsewidth Modulated (PWM) inverters, because of their operation at high frequency, simplicity of turn-off, and low commutation losses compared to the technology using thyristors. But the protection of power transistors, minimization of switching power loss, and design of base drive circuit are very important for a reliable operation of the system. The requirements, analysis, and a simplified procedure for calculation of the switching-aid network components are presented. The transistor is protected against short circuit using a modified autoregulated and autoprotection drive circuit. The experimental results show that the switching power loss and voltage stress in the device can be reduced by suitable choice of the switching-aid network component values.
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Cascaded multilevel inverters synthesize a medium-voltage output based on a series connection of power cells which use standard low-voltage component configurations. This characteristic allows one to achieve high-quality output voltages and input currents and also outstanding availability due to their intrinsic component redundancy. Due to these features, the cascaded multilevel inverter has been recognized as an important alternative in the medium-voltage inverter market. This paper presents a survey of different topologies, control strategies and modulation techniques used by these inverters. Regenerative and advanced topologies are also discussed. Applications where the mentioned features play a key role are shown. Finally, future developments are addressed.
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The low predictive power of implied volatility in forecasting the subsequently realized volatility is a well-documented empirical puzzle. As suggested by e.g. Feinstein (1989), Jackwerth and Rubinstein (1996), and Bates (1997), we test whether unrealized expectations of jumps in volatility could explain this phenomenon. Our findings show that expectations of infrequently occurring jumps in volatility are indeed priced in implied volatility. This has two important consequences. First, implied volatility is actually expected to exceed realized volatility over long periods of time only to be greatly less than realized volatility during infrequently occurring periods of very high volatility. Second, the slope coefficient in the classic forecasting regression of realized volatility on implied volatility is very sensitive to the discrepancy between ex ante expected and ex post realized jump frequencies. If the in-sample frequency of positive volatility jumps is lower than ex ante assessed by the market, the classic regression test tends to reject the hypothesis of informational efficiency even if markets are informationally effective.
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This paper presents a physical explanation of the phenomenon of low frequency oscillations experienced in power systems. A brief account of the present practice of providing fixed gain power system stabilizers (PSS) is followed by a summary of some of the recent design proposals for adaptive PSS. A novel PSS based on the effort of cancelling the negative damping torque produced by the automatic voltage regulator (AVR) is presented along with some recent studies on a multimachine system using a frequency identification technique.
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A new topology of asymmetric cascaded H-Bridge inverter is presented in this paper It consists of two cascaded H-bridge cells per phase. They are fed from isolated dc sources having a dc bus ratio of 1:0.366. Out of many space vectors possible from this circuit, only those are chosen that lie on 12-sided polygons. Thus, the overall space vector diagram produced by this circuit consists of multiple numbers of 12-sided polygons. With a proper PWM timing calculations based on these selected space vectors, it is possible to eliminate all the 6n +/- 1, (n = odd) harmonics from the phase voltage under all operating conditions. The switching frequency of individual H-Bridge cells is also substantially low. Extensive experimental results have been presented in this paper to validate the proposed concept.
Resumo:
The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.
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As aircraft technology is moving towards more electric architecture, use of electric motors in aircraft is increasing. Axial flux BLDC motors (brushless DC motors) are becoming popular in aero application because of their ability to meet the demand of light weight, high power density, high efficiency and high reliability. Axial flux BLDC motors, in general, and ironless axial flux BLDC motors, in particular, come with very low inductance Owing to this, they need special care to limit the magnitude of ripple current in motor winding. In most of the new more electric aircraft applications, BLDC motor needs to be driven from 300 or 600 Vdc bus. In such cases, particularly for operation from 600 Vdc bus, insulated-gate bipolar transistor (IGBT)-based inverters are used for BLDC motor drive. IGBT-based inverters have limitation on increasing the switching frequency, and hence they are not very suitable for driving BLDC motors with low winding inductance. In this study, a three-level neutral point clamped (NPC) inverter is proposed to drive axial flux BLDC motors. Operation of a BLDC motor driven from three-level NPC inverter is explained and experimental results are presented.
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This paper describes the different types of space vector based bus clamped PWM algorithms for three level inverters. A novel bus clamp PWM algorithm for low modulation indices region is also presented. The principles and switching sequences of all the types of bus clamped algorithms for high switching frequency are presented. Synchronized version of the PWM sequences for high power applications where switching frequency is low is also presented. The implementation details on DSP based digital controller and experimental results are presented. The THD of the output waveforms is studied for the entire operating region and is compared with the conventional space vector PWM technique. The bus clamped techniques can be used to reduce the switching losses or to improve the output voltage quality or both.. Different issues dominate depending on the type of application and power rating of the inverters. The results presented in this paper can be used for judicious use of the PWM techniques, which result in improved system efficiency and performance.