Close-quarters Quadrotor flying for a pole inspection with position based visual servoing and high-speed vision

This paper presents a 100 Hz monocular position based visual servoing system to control a quadrotor flying in close proximity to vertical structures approximating a narrow, locally linear shape. Assuming the object boundaries are represented by parallel vertical lines in the image, detection and tracking is achieved using Plücker line representation and a line tracker. The visual information is fused with IMU data in an EKF framework to provide fast and accurate state estimation. A nested control design provides position and velocity control with respect to the object. Our approach is aimed at high performance on-board control for applications allowing only small error margins and without a motion capture system, as required for real world infrastructure inspection. Simulated and ground-truthed experimental results are presented.

Clinoenstatite coatings have high bonding strength, bioactive ion release, and osteoimmunomodulatory effects that enhance in vivo osseointegration

A number of coating materials have been developed over past two decades seeking to improve the osseointegration of orthopedic metal implants. Despite the many candidate materials trialed, their low rate of translation into clinical applications suggests there is room for improving the current strategies for their development. We therefore propose that the ideal coating material(s) should possess the following three properties: (i) high bonding strength, (ii) release of functional ions, and (iii) favourable osteoimmunomodulatory effects. To test this proposal, we developed clinoenstatite (CLT, MgSiO3), which as a coating material has high bonding strength, cytocompability and immunomodulatory effects that are favourable for in vivo osteogenesis. The bonding strength of CLT coatings was 50.1 ± 3.2 MPa, more than twice that of hydroxyapatite (HA) coatings, at 23.5 ± 3.5 MPa. CLT coatings released Mg and Si ions, and compared to HA coatings, induced an immunomodulation more conducive for osseointegration, demonstrated by downregurelation of pro-inflammatory cytokines, enhancement of osteogenesis, and inhibition of osteoclastogenesis. In vivo studies demonstrated that CLT coatings improved osseointegration with host bone, as shown by the enhanced biomechanical strength and increased de novo bone formation, when compared with HA coatings. These results support the notion that coating materials with the proposed properties can induce an in vivo environment better suited for osseointegration. These properties could, therefore, be fundamental when developing high-performance coating materials.

Catalyst engineering for lithium ion batteries: The catalytic role of Ge in enhancing the electrochemical performance of SnO2(GeO2)0.13/G anodes

The catalytic role of germanium (Ge) was investigated to improve the electrochemical performance of tin dioxide grown on graphene (SnO(2)/G) nanocomposites as an anode material of lithium ion batteries (LIBs). Germanium dioxide (GeO(20) and SnO(2) nanoparticles (<10 nm) were uniformly anchored on the graphene sheets via a simple single-step hydrothermal method. The synthesized SnO(2)(GeO(2))0.13/G nanocomposites can deliver a capacity of 1200 mA h g(-1) at a current density of 100 mA g(-1), which is much higher than the traditional theoretical specific capacity of such nanocomposites (∼ 702 mA h g(-1)). More importantly, the SnO(2)(GeO(2))0.13/G nanocomposites exhibited an improved rate, large current capability (885 mA h g(-1) at a discharge current of 2000 mA g(-1)) and excellent long cycling stability (almost 100% retention after 600 cycles). The enhanced electrochemical performance was attributed to the catalytic effect of Ge, which enabled the reversible reaction of metals (Sn and Ge) to metals oxide (SnO(2) and GeO(2)) during the charge/discharge processes. Our demonstrated approach towards nanocomposite catalyst engineering opens new avenues for next-generation high-performance rechargeable Li-ion batteries anode materials.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have implemented a Firewall with this architecture in reconflgurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results in both speed and area improvement when it is implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields. High throughput classification invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly in terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for the worst case packet size. The Firewall rule update involves only memory re-initialization in software without any hardware change.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have Implemented a Firewall with this architecture in reconfigurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using, our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results In both speed and area Improvement when It is Implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields.High throughput classification Invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly In terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware Implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for file worst case packet size. The Firewall rule update Involves only memory re-initialiization in software without any hardware change.

Nonlinear transport in semiconducting polymers at high carrier densities

Conducting and semiconducting polymers are important materials in the development of printed, flexible, large-area electronics such as flat-panel displays and photovoltaic cells. There has been rapid progress in developing conjugated polymers with high transport mobility required for high-performance field-effect transistors (FETs), beginning(1) with mobilities around 10(-4) cm(2) V-1 s(-1) to a recent report(2) of 1 cm(2) V-1 s(-1) for poly(2,5-bis(3-tetradecylthiophen-2-yl) thieno[3,2-b] thiophene) (PBTTT). Here, the electrical properties of PBTTT are studied at high charge densities both as the semiconductor layer in FETs and in electrochemically doped films to determine the transport mechanism. We show that data obtained using a wide range of parameters (temperature, gate-induced carrier density, source-drain voltage and doping level) scale onto the universal curve predicted for transport in the Luttinger liquid description of the one-dimensional `metal'.

Natural convection in rectangular cavities at high Rayleigh number

Natural convection in rectangular two-dimensional cavities with differentially heated side walls is a standard problem in numerical heat transfer. Most of the existing studies has considered the low Ra laminar regime. The general thrust of the present research is to investigate higher Ra flows extending into the unsteady and turbulent regimes where the physics is not fully understood and appropriate models for turbulence are not yet established. In the present study the Boussinesq approximation is being used, but the theoretical background and some preliminary results have been obtained[1] for flows with variable properties.

Bismuth sulfide: A high-capacity anode for sodium-ion batteries

Exploring high-performance anode materials is currently one of the most urgent issues towards practical sodium-ion batteries (SIBs). In this work, Bi2S3 is demonstrated to be a high-capacity anode for SIBs for the first time. The specific capacity of Bi2S3 nanorods achieves up to 658 and 264 mAh g-1 at a current density of 100 and 2000 mA g-1, respectively. A full cell with Na3V2(PO4)3-based cathode is also assembled as a proof of concept and delivers 340 mAh g-1 at 100 mA g-1. The sodium storage mechanism of Bi2S3 is investigated by ex-situ XRD coupled with high-resolution TEM (HRTEM), and it is found that sodium storage is achieved by a combined conversion-intercalation mechanism.

Synergistic crystal facet engineering and structural control of WO3 films exhibiting unprecedented photoelectrochemical performance

WO3 nanoplate arrays with (002) oriented facets grown on fluorine doped SnO2 (FTO) glass substrates are tailored by tuning the precursor solution via a facile hydrothermal method. A 2-step hydrothermal method leads to the preferential growth of WO3 film with enriched (002) facets, which exhibits extraordinary photoelectrochemical (PEC) performance with a remarkable photocurrent density of 3.7 mA cm–2 at 1.23 V vs. revisable hydrogen electrode (RHE) under AM 1.5 G illumination without the use of any cocatalyst, corresponding to ~93% of the theoretical photocurrent of WO3. Density functional theory (DFT) calculations together with experimental studies reveal that the enhanced photocatalytic activity and better photo-stability of the WO3 films are attributed to the synergistic effect of highly reactive (002) facet and nanoplate structure which facilitates the photo–induced charge carrier separation and suppresses the formation of peroxo-species. Without the use of oxygen evolution cocatalysts, the excellent PEC performance, demonstrated in this work, by simply tuning crystal facets and nanostructure of pristine WO3 films may open up new opportunities in designing high performance photoanodes for PEC water splitting.

Exploring energy-performance trade-offs for heterogeneous interconnect clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires which leads to delay in execution and significantly high energy consumption.In this paper, we propose a new instruction scheduling algorithm that exploits scheduling slacks of instructions and communication slacks of data values together to achieve better energy-performance trade-offs for clustered architectures with heterogeneous interconnect. Our instruction scheduling algorithm achieves 35% and 40% reduction in communication energy, whereas the overall energy-delay product improves by 4.5% and 6.5% respectively for 2 cluster and 4 cluster machines with marginal increase (1.6% and 1.1%) in execution time. Our test bed uses the Trimaran compiler infrastructure.

Construction and use of linear regression models for processor performance analysis

Processor architects have a challenging task of evaluating a large design space consisting of several interacting parameters and optimizations. In order to assist architects in making crucial design decisions, we build linear regression models that relate Processor performance to micro-architecture parameters, using simulation based experiments. We obtain good approximate models using an iterative process in which Akaike's information criteria is used to extract a good linear model from a small set of simulations, and limited further simulation is guided by the model using D-optimal experimental designs. The iterative process is repeated until desired error bounds are achieved. We used this procedure to establish the relationship of the CPI performance response to 26 key micro-architectural parameters using a detailed cycle-by-cycle superscalar processor simulator The resulting models provide a significance ordering on all micro-architectural parameters and their interactions, and explain the performance variations of micro-architectural techniques.

Improving Performance of Result Caches in Network Processors

Digest caches have been proposed as an effective method tospeed up packet classification in network processors. In this paper, weshow that the presence of a large number of small flows and a few largeflows in the Internet has an adverse impact on the performance of thesedigest caches. In the Internet, a few large flows transfer a majority ofthe packets whereas the contribution of several small flows to the totalnumber of packets transferred is small. In such a scenario, the LRUcache replacement policy, which gives maximum priority to the mostrecently accessed digest, tends to evict digests belonging to the few largeflows. We propose a new cache management algorithm called SaturatingPriority (SP) which aims at improving the performance of digest cachesin network processors by exploiting the disparity between the number offlows and the number of packets transferred. Our experimental resultsdemonstrate that SP performs better than the widely used LRU cachereplacement policy in size constrained caches. Further, we characterizethe misses experienced by flow identifiers in digest caches.

Adaptive Filtering Technique and DSP Based Implementation for High-Speed Distance Protection

The paper presents an adaptive Fourier filtering technique and a relaying scheme based on a combination of a digital band-pass filter along with a three-sample algorithm, for applications in high-speed numerical distance protection. To enhance the performance of above-mentioned technique, a high-speed fault detector has been used. MATLAB based simulation studies show that the adaptive Fourier filtering technique provides fast tripping for near faults and security for farther faults. The digital relaying scheme based on a combination of digital band-pass filter along with three-sample data window algorithm also provides accurate and high-speed detection of faults. The paper also proposes a high performance 16-bit fixed point DSP (Texas Instruments TMS320LF2407A) processor based hardware scheme suitable for implementation of the above techniques. To evaluate the performance of the proposed relaying scheme under steady state and transient conditions, PC based menu driven relay test procedures are developed using National Instruments LabVIEW software. The test signals are generated in real time using LabVIEW compatible analog output modules. The results obtained from the simulation studies as well as hardware implementations are also presented.

Extended histories: improving regularity and performance in correlation prefetchers

Data Prefetchers identify and make use of any regularity present in the history/training stream to predict future references and prefetch them into the cache. The training information used is typically the primary misses seen at a particular cache level, which is a filtered version of the accesses seen by the cache. In this work we demonstrate that extending the training information to include secondary misses and hits along with primary misses helps improve the performance of prefetchers. In addition to empirical evaluation, we use the information theoretic metric entropy, to quantify the regularity present in extended histories. Entropy measurements indicate that extended histories are more regular than the default primary miss only training stream. Entropy measurements also help corroborate our empirical findings. With extended histories, further benefits can be achieved by triggering prefetches during secondary misses also. In this paper we explore the design space of extended prefetch histories and alternative prefetch trigger points for delta correlation prefetchers. We observe that different prefetch schemes benefit to a different extent with extended histories and alternative trigger points. Also the best performing design point varies on a per-benchmark basis. To meet these requirements, we propose a simple adaptive scheme that identifies the best performing design point for a benchmark-prefetcher combination at runtime. In SPEC2000 benchmarks, using all the L2 accesses as history for prefetcher improves the performance in terms of both IPC and misses reduced over techniques that use only primary misses as history. The adaptive scheme improves the performance of CZone prefetcher over Baseline by 4.6% on an average. These performance gains are accompanied by a moderate reduction in the memory traffic requirements.