DLTS analysis of amphoteric interface defects in high-TiO2 MOS structures prepared by sol-gel spin-coating

High-kappa TiO2 thin films have been fabricated from a facile, combined sol-gel spin - coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO2 with a small grain size of 18 nm. The refractive index `n' quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 angstrom. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO2 were studied by capacitance - voltage (C - V) and deep level transient spectroscopy (DLTS). The flat - band voltage (V-FB) and the density of slow interface states estimated are -0.9, -0.44 V and 5.24x10(10), 1.03x10(11) cm(-2); for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross -sections measured by DLTS are E-V + 0.30, E-C - 0.21 eV; 8.73x10(11), 6.41x10(11) eV(-1) cm(-2) and 5.8x10(-23), 8.11x10(-23) cm(2) for the NMOS and PMOS structures, respectively. A low value of interface state density in both P-and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent. (C) 2015 Author(s).

High-kappa TiO2 Thin Film Prepared by Sol-Gel Spin-Coating Method

High-k TiO2 thin film on p-type silicon substrate was fabricated by a combined sol-gel and spin coating method. Thus deposited titania film had anatase phase with a small grain size of 16 nm and surface roughness of congruent to 0.6 nm. The oxide capacitance (C-ox), flat band capacitance (C-FB), flat band voltage (V-FB), oxide trapped charge (Q(ot)), calculated from the high frequency (1 MHz) C-V curve were 0.47 nF, 0.16 nF, -0.91 V, 4.7x10(-12) C, respectively. As compared to the previous reports, a high dielectric constant of 94 at 1 MHz frequency was observed in the devices investigated here and an equivalent oxide thickness (EOT) was 4.1 nm. Dispersion in accumulation capacitance shows a linear relationship with AC frequencies. Leakage current density was found in acceptable limits (2.1e-5 A/cm(2) for -1 V and 5.7e-7 A/cm(2) for +1 V) for CMOS applications.

High-kappa TiO2 Thin Film Prepared by Sol-Gel Spin-Coating Method

High-k TiO2 thin film on p-type silicon substrate was fabricated by a combined sol-gel and spin coating method. Thus deposited titania film had anatase phase with a small grain size of 16 nm and surface roughness of congruent to 0.6 nm. The oxide capacitance (C-ox), flat band capacitance (C-FB), flat band voltage (V-FB), oxide trapped charge (Q(ot)), calculated from the high frequency (1 MHz) C-V curve were 0.47 nF, 0.16 nF, -0.91 V, 4.7x10(-12) C, respectively. As compared to the previous reports, a high dielectric constant of 94 at 1 MHz frequency was observed in the devices investigated here and an equivalent oxide thickness (EOT) was 4.1 nm. Dispersion in accumulation capacitance shows a linear relationship with AC frequencies. Leakage current density was found in acceptable limits (2.1e-5 A/cm(2) for -1 V and 5.7e-7 A/cm(2) for +1 V) for CMOS applications.

Dielectric investigation of high-k yttrium copper titanate thin films

We report on the first dielectric investigation of high-k yttrium copper titanate thin films, which were demonstrated to be very promising for nanoelectronics applications. The dielectric constant of these films is found to vary from 100 down to 24 (at 100 kHz) as a function of deposition conditions, namely oxygen pressure and film thickness. The physical origin of such variation was investigated in the framework of universal dielectric response and Cole-Cole relations and by means of voltage dependence studies of the dielectric constant. Surface-related effects and charge hopping polarization processes, strictly dependent on the film microstructure, are suggested to be mainly responsible for the observed dielectric response. In particular, the bulky behaviour of thick films deposited at lower oxygen pressure evolves towards a more complex and electrically heterogeneous structure when either the thickness decreases down to 50 nm or the films are grown under high oxygen pressure.

Dielectric investigation of high-k yttrium copper titanate thin films

We report on the first dielectric investigation of high-k yttrium copper titanate thin films, which were demonstrated to be very promising for nanoelectronics applications. The dielectric constant of these films is found to vary from 100 down to 24 (at 100 kHz) as a function of deposition conditions, namely oxygen pressure and film thickness. The physical origin of such variation was investigated in the framework of universal dielectric response and Cole-Cole relations and by means of voltage dependence studies of the dielectric constant. Surface-related effects and charge hopping polarization processes, strictly dependent on the film microstructure, are suggested to be mainly responsible for the observed dielectric response. In particular, the bulky behaviour of thick films deposited at lower oxygen pressure evolves towards a more complex and electrically heterogeneous structure when either the thickness decreases down to 50 nm or the films are grown under high oxygen pressure.

Low temperature solution processed high-kappa ZrO2 gate dielectrics for nanoelectonics

The high-kappa gate dielectrics, specifically amorphous films offer salient features such as exceptional mechanical flexibility, smooth surfaces and better uniformity associated with low leakage current density. In this work, similar to 35 nm thick amorphous ZrO2 films were deposited on silicon substrate at low temperature (300 degrees C, 1 h) from facile spin-coating method and characterized by various analytical techniques. The X-ray diffraction and X-ray photoelectron spectroscopy reveal the formation of amorphous phase ZrO2, while ellipsometry analysis together with the Atomic Force Microscope suggest the formation of dense film with surface roughness of 1.5 angstrom, respectively. The fabricated films were integrated in metal-oxide-semiconductor (MOS) structures to check the electrical capabilities. The oxide capacitance (C-ox), flat band capacitance (C-FB), flat band voltage (V-FB), dielectric constant (kappa) and oxide trapped charges (Q(ot)) extracted from high frequency (1 MHz) C-V curve are 186 pF, 104 pF, 0.37V, 15 and 2 x 10(-11) C, respectively. The small flat band voltage 0.37V, narrow hysteresis and very little frequency dispersion between 10 kHz-1 MHz suggest an excellent a-ZrO2/Si interface with very less trapped charges in the oxide. The films exhibit a low leakage current density 4.7 x 10(-9)A/cm(2) at 1V. In addition, the charge transport mechanism across the MOSC is analyzed and found to have a strong bias dependence. The space charge limited conduction mechanism is dominant in the high electric field region (1.3-5 V) due to the presence of traps, while the trap-supported tunneling is prevailed in the intermediate region (0.35-1.3 V). Low temperature solution processed ZrO2 thin films obtained are of high quality and find their importance as a potential dielectric layer on Si and polymer based flexible electronics. (C) 2016 Published by Elsevier B.V.

Critical investigation of high performance spin-coated high-kappa titania thin films based MOS capacitor

We report the tunable dielectric constant of titania films with low leakage current density. Titanium dioxide (TiO2) films of three different thicknesses (36, 63 and 91 nm) were deposited by the consecutive steps of solution preparation, spin-coating, drying, and firing at different temperatures. The problem of poor adhesion between Si substrate and TiO2 insulating layer was resolved by using the plasma activation process. The surface roughness was found to increase with increasing thickness and annealing temperature. The electrical investigation was carried out using metal-oxide-semiconductor structure. The flat band voltage (V-FB), oxide trapped charge (Q(ot)), dielectric constant (kappa) and equivalent oxide thicknesses are calculated from capacitance-voltage (C-V) curves. The C-V characteristics indicate a thickness dependent dielectric constant. The dielectric constant increases from 31 to 78 as thickness increases from 36 to 91 nm. In addition to that the dielectric constant was found to be annealing temperature and frequency dependent. The films having thickness 91 nm and annealed at 600 A degrees C shows the low leakage current density. Our study provides a broad insight of the processing parameters towards the use of titania as high-kappa insulating layer, which might be useful in Si and polymer based flexible devices.

Arc Voltage Fluctuation in DC Laminar and Turbulent Plasma Jets Generat Ion

Arc voltage fluctuations in a direct current (DC) non-transferred arc plasma generator are experimentally studied, in generating a jet in the laminar, transitional and turbulent regimes. The study is with a view toward elucidating the mechanism of the fluctuations and their relationship with the generating parameters, arc root movement and flow regimes. Results indicate that the existence of a 300 Hz alternating current (AC) component in the power supply ripples does not cause the transition of the laminar plasma jet into a turbulent state. There exists a high frequency fluctuation at 4 kHz in the turbulent jet regime. It may be related to the rapid movement of the anode attachment point of the arc.

High-resolution TEM characterization of ZnO core-shell nanowires for dye-sensitized solar cells

Recently ZnO nanowire films have been used in very promising and inexpensive dye-sensitized solar cells (DSSC). It was found that the performance of the devices can be enhanced by functionalising the nanowires with a thin metal oxide coating. This nm-scale shell is believed to tailor the electronic structure of the nanowire, and help the absorption of the dye. Core-shell ZnO nanowire structures are synthesised at low temperature (below 120°C) by consecutive hydrothermal growth steps. Different materials are investigated for the coating, including Mg, Al, Cs and Zr oxides. High resolution TEM is used to characterise the quality of both the nanowire core and the shell, and to monitor the thickness and the degree of crystallisation of the oxide coating. The interface between the nanowire core and the outer shell is investigated in order to understand the adhesion of the coating, and give valuable feedback for the synthesis process. Nanowire films are packaged into dye-sensitised solar cell prototypes; samples coated with ZrO2 and MgO show the largest enhancement in the photocurrent and open-circuit voltage and look very promising for further improvement. © 2010 IOP Publishing Ltd.

A bulk acoustic mode single-crystal silicon microresonator with a high-quality factor

This paper details a bulk acoustic mode resonator fabricated in single-crystal silicon with a quality factor of 15 000 in air, and over a million below 10 mTorr at a resonant frequency of 2.18 MHz. The resonator is a square plate that is excited in the square-extensional mode and has been fabricated in a commercial foundry silicon-on-insulator (SOI) MEMS process through MEMSCAP. This paper also presents a simple method of extracting resonator parameters from raw measurements heavily buried in electrical feedthrough. Its accuracy has been demonstrated through a comparison between extracted motional resistance values measured at different voltage biases and those predicted from an analytical model. Finally, a method of substantially cancelling electrical feedthrough through system-level electronic implementation is also introduced. © 2008 IOP Publishing Ltd.

Binary excitation of a high-Q bulk acoustic microresonator by actuation polarity inversion

We present a technique for independently exciting two resonant modes of vibration in a single-crystal silicon bulk mode microresonator using the same electrode configuration through control of the polarity of the DC actuation voltage. Applications of this technique may include built-in temperature compensation by the simultaneous selective excitation of two closely spaced modes that may have different temperature coefficients of resonant frequency. The technique is simple and requires minimum circuit overhead for implementation. The technique is implemented on square plate resonators with quality factors as high as 3.06 × 106. Copyright © 2008 by ASME.

Advantages of top-gate, high-k dielectric carbon nanotube field-effect transistors

The subthreshold slope, transconductance, threshold voltage, and hysteresis of a carbon nanotube field-effect transistor (CNT FET) were examined as its configuration was changed from bottom-gate exposed channel, bottom-gate covered channel to top-gate FET. An individual single wall CNT was grown by chemical vapor deposition and its gate configuration was changed while determining its transistor characteristics to ensure that the measurements were not a function of different chirality or diameter CNTs. The bottom-gate exposed CNT FET utilized 900 nm SiO2 as the gate insulator. This CNT FET was then covered with TiO2 to form the bottom-gate covered channel CNT FET. Finally, the top-gate CNT FET was fabricated and the device utilized TiO 2 (K ∼ 80, equivalent oxide thickness=0.25 nm) as the gate insulator. Of the three configurations investigated, the top-gate device exhibited best subthreshold slope (67-70 mV/dec), highest transconductance (1.3 μS), and negligible hysteresis in terms of threshold voltage shift. © 2006 American Institute of Physics.

Fluctuation characteristics of arc voltage and jet flow in a non-transferred dc plasma generated at reduced pressure

A torch with a set of inter-electrode inserts between the cathode and the anode/nozzle with a wide nozzle exit was designed to generate plasma jets at chamber pressures of 500–10 000 Pa. The variation of the arc voltage was examined with the change in working parameters such as gas flow rate and chamber pressure. The fluctuation in the arc voltage was recorded with an oscilloscope, and the plasma jet fluctuation near the torch exit was observed with a high-speed video camera and detected with a double-electrostatic probe. Results show that the 300 Hz wave originated from the tri-phase rectified power supply was always detected under all generating conditions. Helmholtz oscillations over 3000 Hz was detected superposed on the 300 Hz wave at gas flow rates higher than 8.8 slm with a peak to valley amplitude lower than 5% of the average voltage value. No appreciable voltage fluctuation caused by the irregular arc root movement is detected, and mechanisms for the arc voltage and jet flow fluctuations are discussed.

Paths Towards High Efficiency Silicon Photovoltaics

While photovoltaics hold much promise as a sustainable electricity source, continued cost reduction is necessary to continue the current growth in deployment. A promising path to continuing to reduce total system cost is by increasing device efficiency. This thesis explores several silicon-based photovoltaic technologies with the potential to reach high power conversion efficiencies. Silicon microwire arrays, formed by joining millions of micron diameter wires together, were developed as a low cost, low efficiency solar technology. The feasibility of transitioning this to a high efficiency technology was explored. In order to achieve high efficiency, high quality silicon material must be used. Lifetimes and diffusion lengths in these wires were measured and the action of various surface passivation treatments studied. While long lifetimes were not achieved, strong inversion at the silicon / hydrofluoric acid interface was measured, which is important for understanding a common measurement used in solar materials characterization.

Cryogenic deep reactive ion etching was then explored as a method for fabricating high quality wires and improved lifetimes were measured. As another way to reach high efficiency, growth of silicon-germanium alloy wires was explored as a substrate for a III-V on Si tandem device. Patterned arrays of wires with up to 12% germanium incorporation were grown. This alloy is more closely lattice matched to GaP than silicon and allows for improvements in III-V integration on silicon.

Heterojunctions of silicon are another promising path towards achieving high efficiency devices. The GaP/Si heterointerface and properties of GaP grown on silicon were studied. Additionally, a substrate removal process was developed which allows the formation of high quality free standing GaP films and has wide applications in the field of optics.

Finally, the effect of defects at the interface of the amorphous silicon heterojuction cell was studied. Excellent voltages, and thus efficiencies, are achievable with this system, but the voltage is very sensitive to growth conditions. We directly measured lateral transport lengths at the heterointerface on the order of tens to hundreds of microns, which allows carriers to travel towards any defects that are present and recombine. This measurement adds to the understanding of these types of high efficiency devices and may aid in future device design.

A Q-swicthed all-solid-state single-longitudinal-mode laser with adjustable pulse-width and high repetition rate

A single-longitudinal-mode (SLM) laser-diode pumped Nd: YAG laser with adjustable pulse width is developed by using the techniques of pre-lasing and changing polarization of birefingent crystal. The Q-switching voltage is triggered by the peak of the pre-lasing pulse to achieve the higher stability of output pulse energy. The output energy of more than 1 mJ is obtained with output energy stability of 3% (rms) at 100 Hz. The pulse-width can be adjusted from 30 ns to 300 ns by changing the Q-switching voltage. The probability of putting out single-longitudinal-mode pulses is almost 100%. The laser can be run over four hours continually without mode hopping.