996 resultados para program verification


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This article introduces Periodically Controlled Hybrid Automata (PCHA) for modular specification of embedded control systems. In a PCHA, control actions that change the control input to the plant occur roughly periodically, while other actions that update the state of the controller may occur in the interim. Such actions could model, for example, sensor updates and information received from higher-level planning modules that change the set point of the controller. Based on periodicity and subtangential conditions, a new sufficient condition for verifying invariant properties of PCHAs is presented. For PCHAs with polynomial continuous vector fields, it is possible to check these conditions automatically using, for example, quantifier elimination or sum of squares decomposition. We examine the feasibility of this automatic approach on a small example. The proposed technique is also used to manually verify safety and progress properties of a fairly complex planner-controller subsystem of an autonomous ground vehicle. Geometric properties of planner-generated paths are derived which guarantee that such paths can be safely followed by the controller. © 2012 ACM.

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An experimental investigation of a turbine stage featuring very high end wall angles is presented. The initial turbine design did not achieve a satisfactory performance and the difference between the design predictions and the test results was traced to a large separated region on the rear suction-surface. To improve the agreement between computational fluid dynamics (CFD) and experiment, it was found necessary to modify the turbulence modeling employed. The modified CFD code was then used to redesign the vane, and the changes made are described. When tested, the performance of the redesigned vane was found to have much closer agreement with the predictions than the initial vane. Finally, the flowfield and performance of the redesigned stage are compared to a similar turbine, designed to perform the same duty, which lies in an annulus of moderate end wall angles. A reduction in stage efficiency of at least 2.4% was estimated for the very high end wall angle design. © 2014 by ASME.

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A computer program, QtUCP, has been developed based on several well-established algorithms using GCC 4.0 and Qt (R) 4.0 (Open Source Edition) under Debian GNU/Linux 4.0r0. it can determine the unit-cell parameters from an electron diffraction tilt series obtained from both double-tilt and rotation-tilt holders. In this approach, two or more primitive cells of the reciprocal lattice are determined from experimental data, in the meantime, the measurement errors of the tilt angles are checked and minimized. Subsequently, the derived primitive cells are converted into the reduced form and then transformed into the reduced direct primitive cell. Finally all the patterns are indexed and the least-squares refinement is employed to obtain the optimized results of the lattice parameters. Finally, two examples are given to show the application of the program, one is based on the experiment, the other is from the simulation. (C) 2008 Elsevier B.V. All rights reserved.

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An analytical model for the spin filtering transport in a ferromagnetic-metal - Al2O3 - n-type semiconductor tunneling structure has been developed, and demonstrated that the ratio of the helicity-modulated photo-response to the chopped one is proportional to the sum of the relative asymmetry in conductance of two opposite spin-polarized tunneling channels and the MCD effect of the ferromagnetic metal film. The performed measurement in an iron-metal/Al2O3/n-type GaAs tunneling structure under the optical spin orientation has verified that all the aspects of the experimental results are very well in accordance with our model in the regime of the spin filtering. After the MCD effect of the iron film is calibrated by an independent measurement, the physical quantity of Delta G(t)/G(t) (Delta G(t) = G(t)(up arrow) - G(t)(down arrow) is the difference of the conductance between two opposite spin tunneling channels, G(t) =( G(t)(up arrow) + G(t)(down arrow))/2 the averaged tunneling conductance), which concerns us most, can be determined quantitatively with a high sensitivity in the framework of our analytical model. Copyright (c) EPLA, 2008.

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Current-voltage (I-V) characteristics of GaAs-based resonant tunneling diodes have been investigated in the presence of a perpendicular magnetic field. Electron resonant tunneling is strongly suppressed by the applied magnetic field, leading to peak current decreasing with increasing magnetic field. The observed plateau-like structures appear in negative differential resistance region on the I-V curves and are magnetic-field dependent. The plateau-like structures are due to the coupling between the energy levels in the emitter well and in the main quantum well. (C) 2004 American Institute of Physics.

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The performance of the current sensor in power equipment may become worse affected by the environment. In this paper, based on ICA, we propose a method for on-line verification of the phase difference of the current sensor. However, not all source components are mutually independent in our application. In order to get an exact result, we have proposed a relative likelihood index to choose an optimal result from different runs. The index is based on the maximum likelihood evaluation theory and the independent subspace analysis. The feasibility of our method has been confirmed by experimental results.

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This paper introduces a complete CAD toolset for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform. Compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. The FPGA CAD tool verification flow using Formality is presented in detail. Using plug-in technology, we have developed an integrated FPGA design kit to incorporate all tools together.

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In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

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The performance of the current sensor in power equipment may become worse affected by the environment. In this paper, based on ICA, we propose a method for on-line verification of the phase difference of the current sensor. However, not all source components are mutually independent in our application. In order to get an exact result, we have proposed a relative likelihood index to choose an optimal result from different runs. The index is based on the maximum likelihood evaluation theory and the independent subspace analysis. The feasibility of our method has been confirmed by experimental results.