First-principles electronic theory of non-collinear magnetic order in transition-metal nanowires

The structural, electronic and magnetic properties of one-dimensional 3d transition-metal (TM) monoatomic chains having linear, zigzag and ladder geometries are investigated in the frame-work of first-principles density-functional theory. The stability of long-range magnetic order along the nanowires is determined by computing the corresponding frozen-magnon dispersion relations as a function of the 'spin-wave' vector q. First, we show that the ground-state magnetic orders of V, Mn and Fe linear chains at the equilibrium interatomic distances are non-collinear (NC) spin-density waves (SDWs) with characteristic equilibrium wave vectors q that depend on the composition and interatomic distance. The electronic and magnetic properties of these novel spin-spiral structures are discussed from a local perspective by analyzing the spin-polarized electronic densities of states, the local magnetic moments and the spin-density distributions for representative values q. Second, we investigate the stability of NC spin arrangements in Fe zigzag chains and ladders. We find that the non-collinear SDWs are remarkably stable in the biatomic chains (square ladder), whereas ferromagnetic order (q =0) dominates in zigzag chains (triangular ladders). The different magnetic structures are interpreted in terms of the corresponding effective exchange interactions J(ij) between the local magnetic moments μ(i) and μ(j) at atoms i and j. The effective couplings are derived by fitting a classical Heisenberg model to the ab initio magnon dispersion relations. In addition they are analyzed in the framework of general magnetic phase diagrams having arbitrary first, second, and third nearest-neighbor (NN) interactions J(ij). The effect of external electric fields (EFs) on the stability of NC magnetic order has been quantified for representative monoatomic free-standing and deposited chains. We find that an external EF, which is applied perpendicular to the chains, favors non-collinear order in V chains, whereas it stabilizes the ferromagnetic (FM) order in Fe chains. Moreover, our calculations reveal a change in the magnetic order of V chains deposited on the Cu(110) surface in the presence of external EFs. In this case the NC spiral order, which was unstable in the absence of EF, becomes the most favorable one when perpendicular fields of the order of 0.1 V/Å are applied. As a final application of the theory we study the magnetic interactions within monoatomic TM chains deposited on graphene sheets. One observes that even weak chain substrate hybridizations can modify the magnetic order. Mn and Fe chains show incommensurable NC spin configurations. Remarkably, V chains show a transition from a spiral magnetic order in the freestanding geometry to FM order when they are deposited on a graphene sheet. Some TM-terminated zigzag graphene-nanoribbons, for example V and Fe terminated nanoribbons, also show NC spin configurations. Finally, the magnetic anisotropy energies (MAEs) of TM chains on graphene are investigated. It is shown that Co and Fe chains exhibit significant MAEs and orbital magnetic moments with in-plane easy magnetization axis. The remarkable changes in the magnetic properties of chains on graphene are correlated to charge transfers from the TMs to NN carbon atoms. Goals and limitations of this study and the resulting perspectives of future investigations are discussed.

Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic

The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. In this work we present a number of new CMOS logic families, Charge Recovery Logic (CRL) as well as the much improved Split-Level Charge Recovery Logic (SCRL), within which the transfer of charge between the nodes occurs quasistatically. Operating quasistatically, these logic families have an energy dissipation that drops linearly with operating frequency, i.e., their power consumption drops quadratically with operating frequency as opposed to the linear drop of conventional CMOS. The circuit techniques in these new families rely on constructing an explicitly reversible pipelined logic gate, where the information necessary to recover the energy used to compute a value is provided by computing its logical inverse. Information necessary to uncompute the inverse is available from the subsequent inverse logic stage. We demonstrate the low energy operation of SCRL by presenting the results from the testing of the first fully quasistatic 8 x 8 multiplier chip (SCRL-1) employing SCRL circuit techniques.

Reconfigurable Architectures for General-Purpose Computing

General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations. We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space. Our DPGA, a fine- grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite- state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds. Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20x the computational density of conventional processors. Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures.

Cooperative Physics of Fly Swarms: An Emergent Behavior

We have simulated the behavior of several artificial flies, interacting visually with each other. Each fly is described by a simple tracking system (Poggio and Reichardt, 1973; Land and Collett, 1974) which summarizes behavioral experiments in which individual flies fixate a target. Our main finding is that the interaction of theses implemodules gives rise to a variety of relatively complex behaviors. In particular, we observe a swarm-like behavior of a group of many artificial flies for certain reasonable ranges of our tracking system parameters.

New Architectural Models for Visibly Controllable Computing: The Relevance of Dynamic Object Oriented Architectures and Plan Based Computing Models

Traditionally, we've focussed on the question of how to make a system easy to code the first time, or perhaps on how to ease the system's continued evolution. But if we look at life cycle costs, then we must conclude that the important question is how to make a system easy to operate. To do this we need to make it easy for the operators to see what's going on and to then manipulate the system so that it does what it is supposed to. This is a radically different criterion for success. What makes a computer system visible and controllable? This is a difficult question, but it's clear that today's modern operating systems with nearly 50 million source lines of code are neither. Strikingly, the MIT Lisp Machine and its commercial successors provided almost the same functionality as today's mainstream sytsems, but with only 1 Million lines of code. This paper is a retrospective examination of the features of the Lisp Machine hardware and software system. Our key claim is that by building the Object Abstraction into the lowest tiers of the system, great synergy and clarity were obtained. It is our hope that this is a lesson that can impact tomorrow's designs. We also speculate on how the spirit of the Lisp Machine could be extended to include a comprehensive access control model and how new layers of abstraction could further enrich this model.

A Privacy Conscious Bluetooth Infrastructure for Location Aware Computing

We present a low cost and easily deployed infrastructure for location aware computing that is built using standard Bluetooth® technologies and personal computers. Mobile devices are able to determine their location to room-level granularity with existing bluetooth technology, and to even greater resolution with the use of the recently adopted bluetooth 1.2 specification, all while maintaining complete anonymity. Various techniques for improving the speed and resolution of the system are described, along with their tradeoffs in privacy. The system is trivial to implement on a large scale – our network covering 5,000 square meters was deployed by a single student over the course of a few days at a cost of less than US$1,000.

Failure-Oblivious Computing and Boundless Memory Blocks

Memory errors are a common cause of incorrect software execution and security vulnerabilities. We have developed two new techniques that help software continue to execute successfully through memory errors: failure-oblivious computing and boundless memory blocks. The foundation of both techniques is a compiler that generates code that checks accesses via pointers to detect out of bounds accesses. Instead of terminating or throwing an exception, the generated code takes another action that keeps the program executing without memory corruption. Failure-oblivious code simply discards invalid writes and manufactures values to return for invalid reads, enabling the program to continue its normal execution path. Code that implements boundless memory blocks stores invalid writes away in a hash table to return as the values for corresponding out of bounds reads. he net effect is to (conceptually) give each allocated memory block unbounded size and to eliminate out of bounds accesses as a programming error. We have implemented both techniques and acquired several widely used open source servers (Apache, Sendmail, Pine, Mutt, and Midnight Commander).With standard compilers, all of these servers are vulnerable to buffer overflow attacks as documented at security tracking web sites. Both failure-oblivious computing and boundless memory blocks eliminate these security vulnerabilities (as well as other memory errors). Our results show that our compiler enables the servers to execute successfully through buffer overflow attacks to continue to correctly service user requests without security vulnerabilities.

Make progress with physics and chemistry. 'Haz progresos con física y química'.

Seleccionado en la convocatoria: Licencias por estudios destinadas a funcionarios docentes no universitarios, Gobierno de Aragón 2009-10

Methods of Math Physics

Lecture notes for a course on methods of mathematical physics.

School of Mathematics Computing Guide

Guide for computing in the School of Mathematics. Intended for new staff and PG students. Originally written by Anton Prowse from a number of earlier documents.

Reference List for UK Computing Law - INFO2009 - 09/10

Reference List for UK Computing Law

Group Poster for UK Computing Law - INFO2009 - 09/10

Group Poster for UK Computing Law

Resource for UK Computing Law - INFO2009 - 09/10

Zip file containing source code and database dump for the resource

Collection for UK Computing Law - INFO2009 - 09/10

Collection of poster, reference list and resource source and database dump