Designing single event upset mitigation techniques for large SRAM-Based FPGA components

This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Citizens and the future of multilateralism in a polycentric world at 2030: the perspectives of emerging countries for the trading system: the impasse of WTO, the trends of mega agreements, the logic of value chains and the advent of consumers concerns on international trade

A new paradigm is modeling the World: evolutionary innovations in all fronts, new information technologies, huge mobility of capital, use of risky financial tools, globalization of production, new emerging powers and the impact of consumer concerns on governmental policies. These phenomena are shaping the World and forcing the advent of a new World Order in the Multilateral Monetary, Financial, and Trading System. The effects of this new paradigm are also transforming global governance. The political and economic orders established after the World War and centered on the multilateral model of UN, IMF, World Bank, and the GATT, leaded by the developed countries, are facing significant challenges. The rise of China and emerging countries shifted the old model to a polycentric World, where the governance of these organizations are threatened by emerging countries demanding a bigger participation in the role and decision boards of these international bodies. As a consequence, multilateralism is being confronted by polycentrism. Negotiations for a more representative voting process and the pressure for new rules to cope with the new demands are paralyzing important decisions. This scenario is affecting seriously not only the Monetary and Financial Systems but also the Multilateral Trading System. International trade is facing some significant challenges: a serious deadlock to conclude the last round of the multilateral negotiation at the WTO, the fragmentation of trade rules by the multiplication of preferential and mega agreements, the arrival of a new model of global production and trade leaded by global value chains that is threatening the old trade order, and the imposition of new sets of regulations by private bodies commanded by transnationals to support global value chains and non-governmental organizations to reflect the concerns of consumers in the North based on their precautionary attitude about sustainability of products made in the World. The lack of any multilateral order in this new regulation is creating a big cacophony of rules and developing a new regulatory war of the Global North against the Global South. The objective of this paper is to explore how these challenges are affecting the Tradinge System and how it can evolve to manage these new trends.

Lula and Brazil: investors twisted logic

Investors were wrong to believe in change for the better; Brazil is stuck for at least two years