Metastability mechanisms in thin film transistors quantitatively resolved using post-stress relaxation of threshold voltage

A new approach is presented to resolve bias-induced metastability mechanisms in hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs). The post stress relaxation of threshold voltage (V(T)) was employed to quantitatively distinguish between the charge trapping process in gate dielectric and defect state creation in active layer of transistor. The kinetics of the charge de-trapping from the SiN traps is analytically modeled and a Gaussian distribution of gap states is extracted for the SiN. Indeed, the relaxation in V(T) is in good agreement with the theory underlying the kinetics of charge de-trapping from gate dielectric. For the TFTs used in this work, the charge trapping in the SiN gate dielectric is shown to be the dominant metastability mechanism even at bias stress levels as low as 10 V.

Turn-off failure mechanism in large area IGCTs

The destruction mechanism in large area IGCTs (Integrated Gate Commutated Thyristors) under inductive switching conditions is analyzed in detail. The three-dimensional nature of the turn-off process in a 91mm diameter wafer is simulated with a two-dimensional representation. Simulation results show that the final destruction is caused by the uneven dynamic avalanche current distribution across the wafer. © 2011 IEEE.

Integrated avalanche diode for 600 v Trench IGBT over-voltage protection

Avalanche multiplication has been one of the major destructive failure mechanisms in IGBTs; in order to avoid operating an IGBT under abnormal conditions, it is desirable to develop peripheral protecting circuits monolithically integrated without compromising the operation and performance of the IGBT. In this paper, a monolithically integrated avalanche diode (D av) for 600V Trench IGBT over-voltage protection is proposed. The mix-mode transient simulation proves the clamping capability of the D av when the IGBT is experiencing over-voltage stress in unclamped inductive switching (UIS) test. The spread of avalanche energy, which prevents hot-spot formation, through the help of the avalanche diode feeding back a large fraction of the avalanche current to a gate resistance (R G) is also explained. © 2011 IEEE.

IGBT series connection under active voltage control

In this paper an Active Voltage Control (AVC) technique is presented, for series connection of insulated-gate-bipolar-transistors (IGBT) and control of diode recovery. The AVC technique can control the switching trajectory of an IGBT according to a pre-set reference signal. In series connections, every series connected IGBT follows the reference and so that the dynamic voltage sharing is achieved. For the static voltage balancing, the AVC technique can clamp the highest collector-to-emitter voltage to a pre-set clamping voltage level. By selecting the value of the clamping voltage, the difference among series connected IGBTs can be controlled in an accepted range. Another key advantage for AVC is that by changing the reference signal at turn-on, the diode recovery can be optimized. © 2011 EPE Association - European Power Electr.

Transient electrothermal simulation of power semiconductor devices

In this paper, a new thermal model based on the Fourier series solution of heat conduction equation has been introduced in detail. 1-D and 2-D Fourier series thermal models have been programmed in MATLAB/Simulink. Compared with the traditional finite-difference thermal model and equivalent RC thermal network, the new thermal model can provide high simulation speed with high accuracy, which has been proved to be more favorable in dynamic thermal characterization on power semiconductor switches. The complete electrothermal simulation models of insulated gate bipolar transistor (IGBT) and power diodes under inductive load switching condition have been successfully implemented in MATLAB/Simulink. The experimental results on IGBT and power diodes with clamped inductive load switching tests have verified the new electrothermal simulation model. The advantage of Fourier series thermal model over widely used equivalent RC thermal network in dynamic thermal characterization has also been validated by the measured junction temperature.© 2010 IEEE.

Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature

Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of ~10nm Si nanocrystals, separated by SiO 2 regions. At 300 K, strong Coulomb staircases are seen in the drain-source current-voltage (I ds-V ds) characteristics, and single-electron oscillations are seen in the drain-source current-gate voltage (I ds-V ds) characteristics. From 300-20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using singleelectron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction " bottleneck", suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, ~20k BT at 300 K. © 2012 The Japan Society of Applied Physics.

Efficient field emission from triode-type 1D arrays of carbon nanotubes.

Carbon nanotube (CNT) emitters were formed on line-patterned cathodes in microtrenches through a thermal CVD process. Single-walled carbon nanotubes (SWCNTs) self-organized along the trench lines with a submicron inter-CNT spacing. Excellent field emission (FE) properties were obtained: current densities at the anode (J(a)) of 1 microA cm(-2), 10 mA cm(-2) and 100 mA cm(-2) were recorded at gate voltages (V(g)) of 16, 25 and 36 V, respectively. The required voltage difference to gain a 1:10 000 contrast of the anode current was as low as 9 V, indicating that a very low operating voltage is possible for these devices. Not only a large number of emission sites but also the optimal combination of trench structure and emitter morphology are crucial to achieve the full FE potential of thin CNTs with a practical lifetime. The FE properties of 1D arrays of CNT emitters and their optimal design are discussed. Self-organization of thin CNTs is an attractive prospect to tailor preferable emitter designs in FE devices.

Tailoring the morphology of carbon nanotube assemblies using microgradients in the catalyst thickness

In addition to the structural control of individual carbon nanotubes (CNTs), the morphological control of their assemblies is crucial to realize miniaturized CNT devices. Microgradients in the thickness of catalyst are used to enrich the variety of available self-organized morphologies of CNTs. Microtrenches were fabricated in gate/spacer/cathode trilayers using a conventional self-aligned top-down process and catalyst exhibiting a microgradient in its thickness was formed on the cathode by sputter deposition through gate slits. CNTs, including single-walled CNTs, of up to 1μm in length were grown within 5-15 s by chemical vapor deposition. The tendency of thin CNTs to aggregate caused interactions between CNTs with different growth rates, yielding various morphologies dependent on the thickness of the catalyst. The field emission properties of several types of CNT assemblies were evaluated. The ability to produce CNTs with tailored morphologies by engineering the spatial distribution of catalysts will enhance their performance in devices. © 2011 The Japan Society of Applied Physics.

Light-bias induced instability and persistent photoconductivity in In-Zn-O/Ga-In-Zn-O thin film transistors

Stress/recovery measurements demonstrate that even high-performance passivated In-Zn-O/ Ga-In-Zn-O thin film transistors with excellent in-dark stability suffer from light-bias induced threshold voltage shift (ΔV T) and defect density changes. Visible light stress leads to ionisation of oxygen vacancy sites, causing persistent photoconductivity. This makes the material act as though it was n-doped, always causing a negative threshold voltage shift under strong illumination, regardless of the magnitude and polarity of the gate bias.

UV photoconductivity characteristics of ZnO nanowire field effect transistor treated by proton irradiation

We investigated the UV photoconductivity characteristics of ZnO nanowire field effect transistors (FETs) irradiated by proton beams. After proton beam irradiation (using a beam energy of 10 MeV and a fluence of 10 12 cm -2), the drain current and carrier density in the ZnO nanowire FETs decreased, and the threshold voltage shifted to the positive gate bias direction due to the creation of interface traps at the SiO 2/ZnO nanowire interface by the proton beam. The interface traps produced a higher surface barrier potential and a larger depletion region at the ZnO nanowire surface, affecting the photoconductivity and its decay time. The UV photoconductivity of the proton-irradiated ZnO nanowire FETs was higher and more prolonged than that of the pristine ZnO nanowire FETs. The results extend our understanding of the UV photoconductivity characteristics of ZnO nanowire devices and other materials when irradiated with highly energetic particles. © 2012 Elsevier B.V. All rights reserved.

One step self-aligned multilayer patterning process for the fabrication of organic complementary circuits in combination with inkjet printing

Recent development of solution processable organic semiconductors delineates the emergence of a new generation of air-stable, high performance p- and n-type materials. This makes it indeed possible for printed organic complementary circuits (CMOS) to be used in real applications. The main technical bottleneck for organic CMOS to be adopted as the next generation organic integrated circuit is how to deposit and pattern both p- and n-type semiconductor materials with high resolutions at the same time. It represents a significant technical challenge, especially if it can be done for multiple layers without mask alignment. In this paper, we propose a one-step self-aligned fabrication process which allows the deposition and high resolution patterning of functional layers for both p- and n-channel thin film transistors (TFTs) simultaneously. All the dimensional information of the device components is featured on a single imprinting stamp, and the TFT-channel geometry, electrodes with different work functions, p- and n-type semiconductors and effective gate dimensions can all be accurately defined by one-step imprinting and the subsequent pattern transfer process. As an example, we have demonstrated an organic complementary inverter fabricated by 3D imprinting in combination with inkjet printing and the measured electrical characteristics have validated the feasibility of the novel technique. © 2012 Elsevier B.V. All rights reserved.

Temperature dependent electron transport in amorphous oxide semiconductor thin film transistors

A temperature-dependent mobility model in amorphous oxide semiconductor (AOS) thin film transistors (TFTs) extracted from measurements of source-drain terminal currents at different gate voltages and temperatures is presented. At low gate voltages, trap-limited conduction prevails for a broad range of temperatures, whereas variable range hopping becomes dominant at lower temperatures. At high gate voltages and for all temperatures, percolation conduction comes into the picture. In all cases, the temperature-dependent mobility model obeys a universal power law as a function of gate voltage. © 2011 IEEE.

P-16: Light-bias induced instability and persistent photoconductivity in in-zn-o/ga-in-zn-o thin film transistors

Stress/recovery measurements demonstrate that even highperformance passivated In-Zn-O/ Ga-In-Zn-O thin film transistors with excellent in-dark stability suffer from light-bias induced threshold voltage shift (ΔV T) and defect density changes. Visible light stress leads to ionisation of oxygen vacancy sites, causing persistent photoconductivity. This makes the material act as though it was n-doped, always causing a negative threshold voltage shift under strong illumination, regardless of the magnitude and polarity of the gate bias. © 2011 SID.

Low partial pressure chemical vapor deposition of graphene on copper

A systematic study of the Cu-catalyzed chemical vapor deposition of graphene under extremely low partial pressure is carried out. A carbon precursor supply of just P CH4∼ 0.009 mbar during the deposition favors the formation of large-area uniform monolayer graphene verified by Raman spectra. A diluted HNO 3 solution is used to remove Cu before transferring graphene onto SiO 2/Si substrates or carbon grids. The graphene can be made suspended over a ∼12 μm distance, indicating its good mechanical properties. Electron transport measurements show the graphene sheet resistance of ∼0.6 kΩ/□ at zero gate voltage. The mobilities of electrons and holes are ∼1800 cm 2/Vs at 4.2 K and ∼1200 cm 2/Vs at room temperature. © 2011 IEEE.

Experimentally validated three dimensional GCT wafer level simulations

In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models. © 2012 IEEE.