Electrical Hookups and Service Providers in Maine

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Claude Elwood Shannon e a symbolic analysis of relay and switching circuits: tornando o computador uma máquina semiótica.

O nome de Claude Elwood Shannon não é totalmente estranho aos pesquisadores de Comunicação Social. No entanto, parte de sua importância para a história da comunicação no século XX é pouco conhecida. Sua dissertação de mestrado e o artigo dela derivado (A Symbolic Analysis of Relay and Switching Circuits) foram essenciais para que o computador se tornasse uma máquina de comunicação e, conseqüentemente, penetrasse em nossa sociedade na forma como ocorre hoje. Este artigo revisa o primeiro grande trabalho de Shannon e explicita sua participação no contexto atual da comunicação.

Sistema eletro-eletrônico para medição direta de torque em dispositivos girantes utilizando extensômetros de resistência elétrica

Neste trabalho propõe-se um sistema para medição de torque em dispositivos girantes, que utiliza extensômetros de resistência elétrica colados nos próprios elementos constituintes do arranjo mecânico sob análise. Um conjunto de circuitos eletrônicos foi especialmente desenvolvido para o sensoreamento das pequenas deformações que ocorrem nos disposotivos girantes. O sistema opera sem contato eletro-mecânico entre a parte estacionária e a parte girante. Para tanto desenvolveu-se também uma metodologia de projeto e construção de transformadores rotativos que são utilizados para transferência da energia que alimenta os circuitos eletrônicos solidários ao elemento mecânico instrumentado. Também foi necessário utilizar um transmissor em freqüência modulada do sinal elétrico proporcional ao torque medido. Uma análise comparativa, dos resultados obtidos entre os sistemas existentes e aqueles alcançados com a técnica proposta neste trabalho, demonstra sua aplicabilidade em diversas situações práticas.

Functional timing analysis of VLSI circuits containing complex gates

The recent advances in CMOS technology have allowed for the fabrication of transistors with submicronic dimensions, making possible the integration of tens of millions devices in a single chip that can be used to build very complex electronic systems. Such increase in complexity of designs has originated a need for more efficient verification tools that could incorporate more appropriate physical and computational models. Timing verification targets at determining whether the timing constraints imposed to the design may be satisfied or not. It can be performed by using circuit simulation or by timing analysis. Although simulation tends to furnish the most accurate estimates, it presents the drawback of being stimuli dependent. Hence, in order to ensure that the critical situation is taken into account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each combinational block of a circuit as a direct acyclic graph, which is used to estimate the critical delay. First timing analysis tools used only the circuit topology information to estimate circuit delay, thus being referred to as topological timing analyzers. However, such method may result in too pessimistic delay estimates, since the longest paths in the graph may not be able to propagate a transition, that is, may be false. Functional timing analysis, in turn, considers not only circuit topology, but also the temporal and functional relations between circuit elements. Functional timing analysis tools may differ by three aspects: the set of sensitization conditions necessary to declare a path as sensitizable (i.e., the so-called path sensitization criterion), the number of paths simultaneously handled and the method used to determine whether sensitization conditions are satisfiable or not. Currently, the two most efficient approaches test the sensitizability of entire sets of paths at a time: one is based on automatic test pattern generation (ATPG) techniques and the other translates the timing analysis problem into a satisfiability (SAT) problem. Although timing analysis has been exhaustively studied in the last fifteen years, some specific topics have not received the required attention yet. One such topic is the applicability of functional timing analysis to circuits containing complex gates. This is the basic concern of this thesis. In addition, and as a necessary step to settle the scenario, a detailed and systematic study on functional timing analysis is also presented.

Low cost BIST techniques for linear and non-linear analog circuits

With the ever increasing demands for high complexity consumer electronic products, market pressures demand faster product development and lower cost. SoCbased design can provide the required design flexibility and speed by allowing the use of IP cores. However, testing costs in the SoC environment can reach a substantial percent of the total production cost. Analog testing costs may dominate the total test cost, as testing of analog circuits usually require functional verification of the circuit and special testing procedures. For RF analog circuits commonly used in wireless applications, testing is further complicated because of the high frequencies involved. In summary, reducing analog test cost is of major importance in the electronic industry today. BIST techniques for analog circuits, though potentially able to solve the analog test cost problem, have some limitations. Some techniques are circuit dependent, requiring reconfiguration of the circuit being tested, and are generally not usable in RF circuits. In the SoC environment, as processing and memory resources are available, they could be used in the test. However, the overhead for adding additional AD and DA converters may be too costly for most systems, and analog routing of signals may not be feasible and may introduce signal distortion. In this work a simple and low cost digitizer is used instead of an ADC in order to enable analog testing strategies to be implemented in a SoC environment. Thanks to the low analog area overhead of the converter, multiple analog test points can be observed and specific analog test strategies can be enabled. As the digitizer is always connected to the analog test point, it is not necessary to include muxes and switches that would degrade the signal path. For RF analog circuits, this is specially useful, as the circuit impedance is fixed and the influence of the digitizer can be accounted for in the design phase. Thanks to the simplicity of the converter, it is able to reach higher frequencies, and enables the implementation of low cost RF test strategies. The digitizer has been applied successfully in the testing of both low frequency and RF analog circuits. Also, as testing is based on frequency-domain characteristics, nonlinear characteristics like intermodulation products can also be evaluated. Specifically, practical results were obtained for prototyped base band filters and a 100MHz mixer. The application of the converter for noise figure evaluation was also addressed, and experimental results for low frequency amplifiers using conventional opamps were obtained. The proposed method is able to enhance the testability of current mixed-signal designs, being suitable for the SoC environment used in many industrial products nowadays.

Electrical conductivity of soybean seeds after storage in several environments

Membrane integrity, as measured by electrical conductivity (EC), is suggested as an indicator of seed vigor in soybean [Glycine max (L.) Merrill] seeds. This study evaluated the effect of storage time and temperature on EC of six soybean seed lots (two lots each of high, medium and low vigor). All seed lots were adjusted to 120 g kg(-1) seed moisture, sealed in aluminum foil packets and placed in storage at 10 and 20 degreesC or stored unsealed in multi-wall paper bags in warehouse (WH) conditions at Lexington, KY, USA for 486 days. Four of the six seed lots were also stored unsealed at 10 degreesC. All seed lots were sampled at 3-month intervals and evaluated for seed moisture (SMC), standard germination (SG) and vigor [accelerated aging (AA) and EC]. After 91 and 204 days in storage, samples initially stored at 20 degreesC and WH were moved to 10 degreesC and sampled at the same intervals. Seed moisture content for unsealed samples equilibrated at 107 g kg(-1) (+/-9 g kg(-1)) in both the WH and 10 degreesC environments. No change in SG occurred for seeds stored sealed (120 g kg(-1)) at 10 degreesC, except for the low vigor seed lots which declined significantly at the last sample date. The AA germination declined significantly for all, seed lots stored sealed at 10 degreesC, however the EC did not change during the same storage period. Seeds stored sealed at 20 degreesC and unsealed in the WH showed rapid declines in AA and SG and significant increases in EC. When these seeds were moved to 10 degreesC, however, the AA continued to decline while the EC remained at the same level (no significant change) for the remainder of the seed storage period. Thus whilst the AA declined in all environments, the EC only increased at higher temperatures (20 degreesC, WH) but showed little change during storage at 10 degreesC. Thus, precautions must be taken if using EC to measure soybean seed vigor following storage at 10 degreesC.

Electrical conductivity of the seed soaking solution and soybean seedling emergence

Vigor of soybean [Glycine max (L.) Merrill] seeds can be evaluated by measuring the electrical conductivity (EC) of the seed soaking solution, which has shown a satisfactory relationship with field seedling emergence, but has not had aproper definition of range yet. This work studies the relationship between EC and soybean seedling emergence both in the field and laboratory conditions, using twenty two seed lots. Seed water content, standard germination and vigor (EC, accelerated aging and cold tests) were evaluated under laboratory conditions using -0.03; -0.20; -0.40 and -0.60 MPa matric potentials, and field seedling emergence was also observed. There was direct relationship between EC and field seedling emergence (FE). Under laboratory conditions, a decreasing relationship was found between EC and FE as water content in the substrate decreased, Relationships between these two parameters were also found when -0.03; -0.20 and -0.40 MPa matric potentials were used. EC tests can be used successfully to evaluate soybean seed vigor and identify lots with higher or lower field emergence potential.

Seed-borne pathogens and electrical conductivity of soybean seeds

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)