Structural vibration control using resistively shunted piezoceramics

Application of piezoceramic materials in actuation and sensing of vibration is of current interest. Potential and more popular applications of piezoceramics are probably in the field of active vibration control. However, the objective of this work is to investigate the effect of shunted piezoceramics as passive vibration control devices when bonded to a host structure. Resistive shunting of a piezoceramic bonded to a cantilevered duralumin beam has been investigated. The piezoceramic is connected in parallel to an electrical network comprising of resistors and inductors. The piezoceramic is a capacitor that stores and discharges electrical energy that is transformed from the mechanical motion of the structure to which it is bonded. A resistor across the piezoceramic would be termed as a resistively shunted piezoceramic. Similarly, an inductor across the piezoceramic is termed as a resonantly shunted piezoceramic. In this study, the effect of resistive shunting on the nature of damping enhancement to the host structure has been investigated. Analytical studies are presented along with experimental results.

Simulation Blocks for TOSSIM-T2"

We develop several hardware and software simulation blocks for the TinyOS-2 (TOSSIM-T2) simulator. The choice of simulated hardware platform is the popular MICA2 mote. While the hardware simulation elements comprise of radio and external flash memory, the software blocks include an environment noise model, packet delivery model and an energy estimator block for the complete system. The hardware radio block uses the software environment noise model to sample the noise floor.The packet delivery model is built by establishing the SNR-PRR curve for the MICA2 system. The energy estimator block models energy consumption by Micro Controller Unit(MCU), Radio,LEDs, and external flash memory. Using the manufacturer’s data sheets we provide an estimate of the energy consumed by the hardware during transmission, reception and also track several of the MCUs states with the associated energy consumption. To study the effectiveness of this work, we take a case study of a paper presented in [1]. We obtain three sets of results for energy consumption through mathematical analysis, simulation using the blocks built into PowerTossim-T2 and finally laboratory measurements. Since there is a significant match between these result sets, we propose our blocks for T2 community to effectively test their application energy requirements and node life times.

Compiler-Directed Frequency and Voltage Scaling for a Multiple Clock Domain

Multiple Clock Domain processors provide an attractive solution to the increasingly challenging problems of clock distribution and power dissipation. They allow their chips to be partitioned into different clock domains, and each domain’s frequency (voltage) to be independently configured. This flexibility adds new dimensions to the Dynamic Voltage and Frequency Scaling problem, while providing better scope for saving energy and meeting performance demands. In this paper, we propose a compiler directed approach for MCD-DVFS. We build a formal petri net based program performance model, parameterized by settings of microarchitectural components and resource configurations, and integrate it with our compiler passes for frequency selection.Our model estimates the performance impact of a frequency setting, unlike the existing best techniques which rely on weaker indicators of domain performance such as queue occupancies(used by online methods) and slack manifestation for a particular frequency setting (software based methods).We evaluate our method with subsets of SPECFP2000,Mediabench and Mibench benchmarks. Our mean energy savings is 60.39% (versus 33.91% of the best software technique)in a memory constrained system for cache miss dominated benchmarks, and we meet the performance demands.Our ED2 improves by 22.11% (versus 18.34%) for other benchmarks. For a CPU with restricted frequency settings, our energy consumption is within 4.69% of the optimal.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

Bioenergy Status of Sharavathi River Basin, Western Ghats, India

Most of the developing countries including India depend heavily on bioenergy and it accounts for about 15% of the global energy usage. Its role in meeting a region’s requirement has increased the interest of assessing the status of biomass availability in a region. The present work deals with the bioenergy status in the Linganamakki reservoir catchment of the Sharavathi river basin, Western Ghats,India, by assessing the energy supply and sector wise energy consumption. The study reveals that majority of the households (92.17%) depend on fuelwood for their domestic energy needs with the per capita fuelwood consumption of 1.2 tonnes/year, which is higher than the national average (0.7 tonnes/year). This higher dependence on fuelwood has contributed to the degradation of forests,resulting in scarcity of bioresources necessitating exploration of viable energy alternatives to meet the growing energy demand.

Geographical Information System Approach for Regional Biogas Potential Assessment

The economic prosperity and quality of life in a region are closely linked to the level of its per capita energy consumption. In India more than 70% of the total population inhabits rural areas and 85-90% of energy requirement is being met by bioresources. With dwindling resources, attention of planners is diverted to viable energy alternatives to meet the rural energy demand. Biogas as fuel is one such alternative, which can be obtained by anaerobic digestion of animal residues and domestic and farm wastes, abundantly available in the countryside. Study presents the techniques to assess biogas potential spatially using GIS in Kolar district, Karnataka State, India. This would help decision makers in selecting villages for implementing biogas programmes based on resource availability. Analyses reveal that the domestic energy requirement of more than 60% population can be met by biogas option. This is based on the estimation of the per capita requirement of gas for domestic purposes and availability of livestock residues.

An Efficient Scheme for Establishing Pairwise Keys for Wireless Sensor Networks

This paper addresses the problem of secure path key establishment in wireless sensor networks that uses the random key pre-distribution technique. Inspired by the recent proxy-based scheme in the work of Ling and Znati (2005) and Li et al. (2005), we introduce a friend-based scheme for establishing pairwise keys securely. We show that the chances of finding friends in a neighbourhood are considerably more than that of finding proxies, leading to lower communication overhead. Further, we prove that the friend-based scheme performs better than the proxy-based scheme both in terms of resilience against node capture as well as in energy consumption for pairwise key establishment, making our scheme more feasible.

Compiler-Directed Dynamic Voltage Scaling using Program Phases

Energy consumption has become a major constraint in providing increased functionality for devices with small form factors. Dynamic voltage and frequency scaling has been identified as an effective approach for reducing the energy consumption of embedded systems. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. This paper concentrates on coarser program regions and for the first time uses program phase behavior for performing dynamic voltage scaling. Program phases are annotated at compile time with mode switch instructions. Further, we relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple integer linear program formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains a 38% reduction in energy consumption on an average, with a performance degradation of 1% and upto 45% reduction in energy with a performance degradation of 5%. Further, the energy consumed by the heuristic solution is within 1% of the optimal solution obtained from the ILP approach.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

A Scalable Low Power Issue Queue for Large Instruction Window Processors

Large instruction windows and issue queues are key to exploiting greater instruction level parallelism in out-of-order superscalar processors. However, the cycle time and energy consumption of conventional large monolithic issue queues are high. Previous efforts to reduce cycle time segment the issue queue and pipeline wakeup. Unfortunately, this results in significant IPC loss. Other proposals which address energy efficiency issues by avoiding only the unnecessary tag-comparisons do not reduce broadcasts. These schemes also increase the issue latency.To address both these issues comprehensively, we propose the Scalable Lowpower Issue Queue (SLIQ). SLIQ augments a pipelined issue queue with direct indexing to mitigate the problem of delayed wakeups while reducing the cycle time. Also, the SLIQ design naturally leads to significant energy savings by reducing both the number of tag broadcasts and comparisons required.A 2 segment SLIQ incurs an average IPC loss of 0.2% over the entire SPEC CPU2000 suite, while achieving a 25.2% reduction in issue latency when compared to a monolithic 128-entry issue queue for an 8-wide superscalar processor. An 8 segment SLIQ improves scalability by reducing the issue latency by 38.3% while incurring an IPC loss of only 2.3%. Further, the 8 segment SLIQ significantly reduces the energy consumption and energy-delay product by 48.3% and 67.4% respectively on average.

Enhanced Performance of Discharge Plasma in Raw Engine Exhaust Treatment-Operation under Different Temperatures and Loads

This paper reports improved performance of discharge plasma in raw engine exhaust treatment. For the purpose of investigation, both filtered and raw diesel engine exhaust were separately treated by the discharge plasma. In raw exhaust environment, the discharge plasma exhibits a superior performance with regard to NOx removal, energy consumption and formation of by-products. In this study, experiments were conducted at conditions of different temperatures and loads.

Experiments on and thermodynamic analysis of a turbocharged engine with producer gas as fuel

This article presents the studies conducted on turbocharged producer gas engines designed originally for natural gas (NG) as the fuel. Producer gas, whose properties like stoichiometric ratio, calorific value, laminar flame speed, adiabatic flame temperature, and related parameters that differ from those of NG, is used as the fuel. Two engines having similar turbochargers are evaluated for performance. Detailed measurements on the mass flowrates of fuel and air, pressures and temperatures at various locations on the turbocharger were carried out. On both the engines, the pressure ratio across the compressor was measured to be 1.40 +/- 0.05 and the density ratio to be 1.35 +/- 0.05 across the turbocharger with after-cooler. Thermodynamic analysis of the data on both the engines suggests a compressor efficiency of 70 per cent. The specific energy consumption at the peak load is found to be 13.1 MJ/kWh with producer gas as the fuel. Compared with the naturally aspirated mode, the mass flow and the peak load in the turbocharged after-cooled condition increased by 35 per cent and 30 per cent, respectively. The pressure ratios obtained with the use of NG and producer gas are compared with corrected mass flow on the compressor map.

Shape Effect on Electronic and Photovoltaic Properties of CdS Nanocrystals

Changes in electronic and photovoltaic properties of semiconductor nanocrystals predominantly due to changes in shape are discussed here. Cadmium sulfide (CdS) semiconductor nanocrystals of various shapes (tetrapod, tetrahedron, sphere and rod) obtained using an optimized solvothermal process exhibited a mixed cubic (zinc blende) and hexagonal (wurtzite) crystal structure. The simultaneous presence of the two crystal phases in varying amounts is observed to play a pivotal role in determining both the electronic and photovoltaic properties of the CdS nanocrystals. Light to electrical energy conversion efficiencies (measured in two-electrode configuration laboratory solar cells) remarkably decreased by one order in magnitude from tetrapod -> tetrahedron -> sphere -> rod. The tetrapod-CdS nanocrystals, which displayed the highest light to electrical energy conversion efficiency, showed a favorable shift in position of the conduction band edge leading to highest rate of electron injection (from CdS nanocrystal to the wide band gap semiconductor viz, titanium dioxide, TiO2) and lowest rate of electron-hole recombination (higher free electron lifetimes).

Decentralised carbon footprint analysis for opting climate change mitigation strategies in India

Carbon footprint (CF) refers to the total amount of carbon dioxide and its equivalents emitted due to various anthropogenic activities. Carbon emission and sequestration inventories have been reviewed sector-wise for all federal states in India to identify the sectors and regions responsible for carbon imbalances. This would help in implementing appropriate climate change mitigation and management strategies at disaggregated levels. Major sectors of carbon emissions in India are through electricity generation, transport, domestic energy consumption, industries and agriculture. A majority of carbon storage occurs in forest biomass and soil. This paper focuses on the statewise carbon emissions (CO2. CO and CH4), using region specific emission factors and statewise carbon sequestration capacity. The estimate shows that CO2, CO and CH4 emissions from India are 965.9, 22.5 and 16.9 Tg per year, respectively. Electricity generation contributes 35.5% of total CO2 emission, which is followed by the contribution from transport. Vehicular transport exclusively contributes 25.5% of total emission. The analysis shows that Maharashtra emits higher CO2, followed by Andhra Pradesh, Uttar Pradesh, Gujarat, Tamil Nadu and West Bengal. The carbon status, which is the ratio of annual carbon storage against carbon emission, for each federal state is computed. This shows that small states and union territories (UT) like Arunachal Pradesh, Mizoram and Andaman and Nicobar Islands, where carbon sequestration is higher due to good vegetation cover, have carbon status > 1. Annually, 7.35% of total carbon emissions get stored either in forest biomass or soil, out of which 34% is in Arunachal Pradesh, Madhya Pradesh, Chhattisgarh and Orissa. (C) 2012 Elsevier Ltd. All rights reserved.

Electrochemical capacitors: Technical challenges and prognosis for future markets

Electrochemical capacitors are potential devices that could help bringing about major advances in future energy storage. They are lightweight and their manufacture and disposal has no detrimental effects on the environment. A comprehensive description of fundamental science of electrochemical capacitors is presented. Similarities and differences between electrochemical capacitors and secondary batteries for electrical energy storage are highlighted and various types of electrochemical capacitors are discussed with special reference to lead-carbon hybrid ultracapacitors. Some envisaged applications of electrochemical capacitors are described along with the technical challenges and prognosis for future markets. (C) 2012 Published by Elsevier Ltd.