Desarrollo de un modelo de riesgo de colisión en espacios aéreos de área terminal

El transporte aéreo es un sector estratégico para el crecimiento económico de cualquier país. La estabilidad y el desarrollo de este modo de transporte tienen un pilar fundamental en una operación segura, especialmente cuando las previsiones indican escenarios de crecimiento continuo del tráfico aéreo. La estimación del riesgo y, por tanto, del nivel de seguridad de un entorno operativo se ha basado en métodos indirectos como puede ser la cuantificación y análisis de los reportes voluntarios de incidentes o el uso de modelos de riesgo de colisión enfocados a escenarios operativos parciales, como puede ser un espacio aéreo oceánico. La operación en un área terminal de maniobra es compleja, con distintos flujos de tráfico de arribada y salida a uno o varios aeropuertos, con cambios frecuentes en el rumbo y velocidad de las aeronaves y con instrucciones tácticas del control de tráfico aéreo para secuenciar y separar las aeronaves El objetivo de la presente Tesis es complementar los actuales métodos de monitorización de la seguridad que presentan sus limitaciones, con el desarrollo de un modelo de riesgo de colisión para áreas terminales de alta densidad que se base en datos objetivos como son las trazar radar de las aeronaves y que tenga en cuenta la complejidad de la operación en un área terminal. Para evaluar el modelo desarrollado se ha implementado una herramienta prototipo en MATLAB© que permite procesar un número masivo de trazar radar para un escenario de área terminal y calcular un valor del riesgo de colisión para el escenario analizado. El prototipo ha sido utilizado para estimar la probabilidad de colisión para distintos escenarios del área terminal de Madrid. El uso de trazas radar permite monitorizar el nivel de riesgo de escenarios reales de manera periódica estableciendo niveles de alerta temprana si se detecta que el valor de riesgo se desvía en exceso, pero también permite evaluar el nivel de riesgo de diseños de espacio aéreo o de nuevos modos de operación a partir de las trazas radar obtenidas en las simulaciones en tiempo real o acelerado y actuar en fases tempranas de los proyectos. ABSTRACT The air transport is a strategic sector for the economic growth of any country. The stability and development of the transport mode have a fundamental pillar in a safe operation, especially when long-term forecasts show scenarios of continuous growth in air traffic. Risk estimation and therefore the level of safety in an operational airspace has been based on indirect methods such as the quantification and analysis of voluntary reports of safety incidents or use of collision risk models focused on partial or simple operational scenarios such as an oceanic airspace. The operation on a terminal maneuvering area is complex, with different traffic flows of arrival and departure at one or more airports, with frequent changes in direction and speed of aircraft and tactical instructions of air traffic control to sequence and separate aircraft. The objective of this Thesis is to complement existing methods of monitoring safety that have their limitations, with the development of a collision risk model for high-density terminal areas that is based on objective data such as aircraft radar tracks and taking into account the complexity of the operation in a terminal area. To evaluate the developed model a prototype tool was implemented with MATLAB© that can process massive numbers of radar tracks for a terminal area scenario and computing a collision risk value for that scenario. The prototype has been used to estimate the probability of collision for different scenarios of the terminal area of Madrid. The use of radar tracks allows to monitor the level of risk of real scenarios periodically establishing levels of early warning when the risk value deviates too much, but also to assess the risk level of airspace designs or modes of operations from the radar tracks obtained in real or fast time simulations and act in the early stages of projects.

Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento específicos que realizan una tarea fija durante toda su vida útil. Para cumplir con requisitos estrictos de coste, tamaño y peso, el equipo de diseño debe optimizar su funcionamiento para condiciones muy específicas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento más inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operación cada vez más dinámicos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo diseño tales como: cambios en las características de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de cómputo, por ejemplo debido a fallos o defectos de fabricación; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema dinámicos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptación autónoma sin intervención humana a lo largo de la vida útil, permitiendo que tomen sus propias decisiones en tiempo de ejecución. Éstos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras características, las de auto-configuración, auto-optimización y auto-reparación. Típicamente, la parte soft de un sistema es mayoritariamente la única utilizada para proporcionar algunas capacidades de adaptación a un sistema. Sin embargo, la proporción rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones está siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia también aumente. Además, la mejora en metodologías de diseño no ha sido acorde como para poder utilizar toda la capacidad de cómputo disponible proporcionada por los núcleos. Por todo ello, no se están satisfaciendo adecuadamente las demandas de cómputo que imponen las nuevas aplicaciones. La solución tradicional para mejorar la proporción rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producción en masa y además la naturaleza estática de su estructura complica la solución a las necesidades de adaptación. Los avances en tecnologías de fabricación han hecho que la FPGA, una vez lenta y pequeña, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de cómputo reconfigurable de gran potencia, con una cantidad enorme de recursos lógicos computacionales y cores hardware empotrados de procesamiento de señal y de propósito general. Sus capacidades de reconfiguración han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado más como estático. El motivo es que como en el caso de las FPGAs basadas en tecnología SRAM, la reconfiguración parcial dinámica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecución mientras el resto permanecen activos. Además, este proceso de reconfiguración puede ser ejecutado internamente por el propio dispositivo. El avance tecnológico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computación Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicación más exóticos y menos convencionales que ha posibilitado la computación reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a través de reconfiguración en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biológicas naturales, que guía la dirección del cambio. Es una aplicación más del campo de la Computación Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimización global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resolución de problemas. En analogía al proceso biológico de la evolución, en el hardware evolutivo el sujeto de la evolución es una población de circuitos que intenta adaptarse a su entorno mediante una adecuación progresiva generación tras generación. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuación (o fitness) después de ser evaluados, y usándolos como padres de la siguiente generación, el algoritmo evolutivo crea una nueva población hija usando operadores genéticos como la mutación y la recombinación. Según se van sucediendo generaciones, se espera que la población en conjunto se aproxime a la solución óptima al problema de encontrar una configuración del circuito adecuada que satisfaga las especificaciones. El estado de la tecnología de reconfiguración después de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obstáculo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos públicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguración lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los años 2000 permitió mantener la investigación en el campo mientras la tecnología de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que actúa como un circuito reconfigurable de aplicación específica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguración y aumenta su velocidad (comparada con la reconfiguración nativa). Es un array de nodos computacionales especificados usando descripciones HDL estándar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a través de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande actúa como memoria de configuración, por lo que la reconfiguración del VRC es muy rápida ya que tan sólo implica la escritura de este registro, el cual controla las señales de selección del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de área debido a la implementación simultánea de cada función en cada nodo del array más los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento máxima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigación sobre sistemas auto-adaptativos. Combinar un sustrato de cómputo auto-reconfigurable capaz de ser modificado dinámicamente en tiempo de ejecución con un algoritmo empotrado que proporcione una dirección de cambio, puede ayudar a satisfacer los requisitos de adaptación autónoma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis está por tanto dirigida a contribuir a la auto-adaptación del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de parámetros soft. De esta distinción, se derivan dos lineas de trabajo. Por un lado, auto-adaptación paramétrica, y por otro auto-adaptación estructural. El objetivo perseguido en el caso de la auto-adaptación paramétrica es la implementación de técnicas de optimización evolutiva complejas en sistemas empotrados con recursos limitados para la adaptación paramétrica online de circuitos de procesamiento de señal. La aplicación seleccionada como prueba de concepto es la optimización para tipos muy específicos de imágenes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresión de imágenes. Por tanto, el objetivo requerido de la evolución es una compresión adaptativa y más eficiente comparada con los procedimientos estándar. El principal reto radica en reducir la necesidad de recursos de supercomputación para el proceso de optimización propuesto en trabajos previos, de modo que se adecúe para la ejecución en sistemas empotrados. En cuanto a la auto-adaptación estructural, el objetivo de la tesis es la implementación de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguración nativas. En este caso, la prueba de concepto es la evolución de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detección de bordes en la imagen. En general, el objetivo es la evolución en tiempo de ejecución de tareas de procesamiento de imagen desconocidas en tiempo de diseño (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporación de DPR en EHW para evolucionar la arquitectura de un array sistólico adaptable mediante reconfiguración cuya capacidad de evolución no había sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptación (AE, Adaptation Engine), un motor de reconfiguración (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptación paramétrica, la plataforma propuesta está caracterizada por: • un CE caracterizado por un núcleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet • un algoritmo evolutivo como AE que busca filtros wavelet candidatos a través de un proceso de optimización paramétrica desarrollado específicamente para sistemas caracterizados por recursos de procesamiento limitados • un nuevo operador de mutación simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluación rápida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la búsqueda evolutiva asociada a la adaptación de wavelets. En el caso de adaptación estructural, la plataforma propuesta toma la forma de: • un CE basado en una plantilla de array sistólico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables • un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecución • un RE hardware que explota la capacidad de reconfiguración nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecución • una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posición, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: • Una plataforma evolutiva basada en FPGA para la auto-adaptación paramétrica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptación (AE) evolutivo y un motor de reconfiguración (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptación paramétrica y estructural. • En cuanto a la auto-adaptación paramétrica, las contribuciones principales son: – Un motor computacional adaptable mediante registros que permite la adaptación paramétrica de los coeficientes de una implementación hardware adaptativa de un núcleo de DWT. – Un motor de adaptación basado en un algoritmo evolutivo desarrollado específicamente para optimización numérica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. – Un núcleo IP de DWT auto-adaptativo en tiempo de ejecución para sistemas empotrados que permite la optimización online del rendimiento de la transformada para compresión de imágenes en entornos específicos de despliegue, caracterizados por tipos diferentes de señal de entrada. – Un modelo software y una implementación hardware de una herramienta para la construcción evolutiva automática de transformadas wavelet específicas. • Por último, en cuanto a la auto-adaptación estructural, las contribuciones principales son: – Un motor computacional adaptable mediante reconfiguración nativa de FPGAs caracterizado por una plantilla de array sistólico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de cómputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. – Definición de una biblioteca de elementos de procesamiento apropiada para la síntesis autónoma en tiempo de ejecución de diferentes tareas de procesamiento de imagen. – Incorporación eficiente de la reconfiguración parcial dinámica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo también se comparan originalmente los detalles de implementación de ambas propuestas. – Una plataforma tolerante a fallos, auto-curativa, que permite la recuperación funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguración, se hace un análisis sistemático de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. – Una plataforma con calidad de filtrado dinámica que permite la adaptación online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, también se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes dinámicamente. Este documento está organizado en cuatro partes y nueve capítulos. La primera parte contiene el capítulo 1, una introducción y motivación sobre este trabajo de tesis. A continuación, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el capítulo 2 contiene una introducción a los conceptos de auto-adaptación y computación autonómica (autonomic computing) como un campo de investigación más general que el muy específico de este trabajo; el capítulo 3 introduce la computación evolutiva como la técnica para dirigir la adaptación; el capítulo 4 analiza las plataformas de computación reconfigurables como la tecnología para albergar hardware auto-adaptativo; y finalmente, el capítulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el capítulo 6 contiene una declaración de los objetivos de la tesis y la descripción de la propuesta en su conjunto, los capítulos 7 y 8 abordan la auto-adaptación paramétrica y estructural, respectivamente. Finalmente, el capítulo 9 de la parte 4 concluye el trabajo y describe caminos de investigación futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: • a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients • an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources • a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: • a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes • an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library • a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time • a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. • An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. • Regarding parametric self-adaptation, main contributions are: – A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. – An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. – A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. – A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. • Lastly, regarding structural self-adaptation, main contributions are: – A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. – Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. – Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. – A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. – A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.

Thermal adaptation analyzed by comparison of protein sequences from mesophilic and extremely thermophilic Methanococcus species

The genome sequence of the extremely thermophilic archaeon Methanococcus jannaschii provides a wealth of data on proteins from a thermophile. In this paper, sequences of 115 proteins from M. jannaschii are compared with their homologs from mesophilic Methanococcus species. Although the growth temperatures of the mesophiles are about 50°C below that of M. jannaschii, their genomic G+C contents are nearly identical. The properties most correlated with the proteins of the thermophile include higher residue volume, higher residue hydrophobicity, more charged amino acids (especially Glu, Arg, and Lys), and fewer uncharged polar residues (Ser, Thr, Asn, and Gln). These are recurring themes, with all trends applying to 83–92% of the proteins for which complete sequences were available. Nearly all of the amino acid replacements most significantly correlated with the temperature change are the same relatively conservative changes observed in all proteins, but in the case of the mesophile/thermophile comparison there is a directional bias. We identify 26 specific pairs of amino acids with a statistically significant (P < 0.01) preferred direction of replacement.

PRIM: Proximity imaging of green fluorescent protein-tagged polypeptides

We report a serendipitous discovery that extends the impressive catalog of reporter functions performed by green fluorescent protein (GFP) or its derivatives. When two GFP molecules are brought into proximity, changes in the relative intensities of green fluorescence emitted upon excitation at 395 vs. 475 nm result. These spectral changes provide a sensitive ratiometric index of the extent of self-association that can be exploited to quantitatively image homo-oligomerization or clustering processes of GFP-tagged proteins in vivo. The method, which we term proximity imaging (PRIM), complements fluorescence resonance energy transfer between a blue fluorescent protein donor and a GFP acceptor, a powerful method for imaging proximity relationships between different proteins. However, unlike fluorescence resonance energy transfer (which is a spectral interaction), PRIM depends on direct contact between two GFP modules, which can lead to structural perturbations and concomitant spectral changes within a module. Moreover, the precise spatial arrangement of the GFP molecules within a given dimer determines the magnitude and direction of the spectral change. We have used PRIM to detect FK1012-induced dimerization of GFP fused to FK506-binding protein and clustering of glycosylphosphatidylinositol-anchored GFP at cell surfaces.

Neural systems underlying learning and representation of global motion

We demonstrate performance-related changes in cortical and cerebellar activity. The largest learning-dependent changes were observed in the anterior lateral cerebellum, where the extent and intensity of activation correlated inversely with psychophysical performance. After learning had occurred (a few minutes), the cerebellar activation almost disappeared; however, it was restored when the subjects were presented with a novel, untrained direction of motion for which psychophysical performance also reverted to chance level. Similar reductions in the extent and intensity of brain activations in relation to learning occurred in the superior colliculus, anterior cingulate, and parts of the extrastriate cortex. The motion direction-sensitive middle temporal visual complex was a notable exception, where there was an expansion of the cortical territory activated by the trained stimulus. Together, these results indicate that the learning and representation of visual motion discrimination are mediated by different, but probably interacting, neuronal subsystems.

Centrosome positioning and directionality of cell movements

In several cell types, an intriguing correlation exists between the position of the centrosome and the direction of cell movement: the centrosome is located behind the leading edge, suggesting that it serves as a steering device for directional movement. A logical extension of this suggestion is that a change in the direction of cell movement is preceded by a reorientation, or shift, of the centrosome in the intended direction of movement. We have used a fusion protein of green fluorescent protein (GFP) and γ-tubulin to label the centrosome in migrating amoebae of Dictyostelium discoideum, allowing us to determine the relationship of centrosome positioning and the direction of cell movement with high spatial and temporal resolution in living cells. We find that the extension of a new pseudopod in a migrating cell precedes centrosome repositioning. An average of 12 sec elapses between the initiation of pseudopod extension and reorientation of the centrosome. If no reorientation occurs within approximately 30 sec, the pseudopod is retracted. Thus the centrosome does not direct a cell’s migration. However, its repositioning stabilizes a chosen direction of movement, most probably by means of the microtubule system.

An extracellular signaling component in propagation of astrocytic calcium waves

Focally evoked calcium waves in astrocyte cultures have been thought to propagate by gap-junction-mediated intercellular passage of chemical signal(s). In contrast to this mechanism we observed isolated astrocytes, which had no physical contact with other astrocytes in the culture, participating in a calcium wave. This observation requires an extracellular route of astrocyte signaling. To directly test for extracellular signaling we made cell-free lanes 10–300 μm wide in confluent cultures by deleting astrocytes with a glass pipette. After 4–8 hr of recovery, regions of confluent astrocytes separated by lanes devoid of cells were easily located. Electrical stimulation was used to initiate calcium waves. Waves crossed narrow (<120 μm) cell-free lanes in 15 of 36 cases, but failed to cross lanes wider than 120 μm in eight of eight cases. The probability of crossing narrow lanes was not correlated with the distance from the stimulation site, suggesting that cells along the path of the calcium wave release the extracellular messenger(s). Calculated velocity across the acellular lanes was not significantly different from velocity through regions of confluent astrocytes. Focal superfusion altered both the extent and the direction of calcium waves in confluent regions. These data indicate that extracellular signals may play a role in astrocyte–astrocyte communication in situ.

Orientation of the transcription preinitiation complex in Archaea

The basal transcription machinery of Archaea corresponds to the minimal subset of factors required for RNA polymerase II transcription in eukaryotes. Using just two factors, Archaea recruit the RNA polymerase to promoters and define the direction of transcription. Notably, the principal determinant for the orientation of transcription is not the recognition of the TATA box by the TATA-box-binding protein. Instead, transcriptional polarity is governed by the interaction of the archaeal TFIIB homologue with a conserved motif immediately upstream of the TATA box. This interaction yields an archaeal preinitiation complex with the same orientation as the analogous eukaryal complex.

The structural basis for the oriented assembly of a TBP/TFB/promoter complex

Recently the definition of the metazoan RNA polymerase II and archaeal core promoters has been expanded to include a region immediately upstream of the TATA box called the B recognition element (BRE), so named because eukaryal transcription factor TFIIB and its archaeal orthologue TFB interact with the element in a sequence-specific manner. Here we present the 2.4-Å crystal structure of archaeal TBP and the C-terminal core of TFB (TFBc) in a complex with an extended TATA-box-containing promoter that provides a detailed picture of the stereospecific interactions between the BRE and a helix–turn–helix motif in the C-terminal cyclin repeat of TFBc. This interaction is important in determining the level of basal transcription and explicitly defines the direction of transcription.

Role of intrinsic synaptic circuitry in collicular sensorimotor integration

The superficial gray layer of the superior colliculus contains a map that represents the visual field, whereas the underlying intermediate gray layer contains a vector map of the saccades that shift the direction of gaze. These two maps are aligned so that a particular region of the visual field is represented directly above the neurons that orient the highest acuity area of the retina toward that region. Although it has been proposed that the transmission of information from the visuosensory to the motor map plays an important role in the generation of visually guided saccades, experiments have failed to demonstrate any functional linkage between the two layers. We examined synaptic transmission between these layers in vitro by stimulating the superficial layer while using whole-cell patch-clamp methods to measure the responses of intermediate layer neurons. Stimulation of superficial layer neurons evoked excitatory postsynaptic currents in premotor cells. This synaptic input was columnar in organization, indicating that the connections between the layers link corresponding regions of the visuosensory and motor maps. Excitatory postsynaptic currents were large enough to evoke action potentials and often occurred in clusters similar in duration to the bursts of action potentials that premotor cells use to command saccades. Our results indicate the presence of functional connections between the superficial and intermediate layers and show that such connections could play a significant role in the generation of visually guided saccades.

Real-Time Imaging of the Axonal Transport of Granules Containing a Tissue Plasminogen Activator/Green Fluorescent Protein Hybrid

A hybrid protein, tPA/GFP, consisting of rat tissue plasminogen activator (tPA) and green fluorescent protein (GFP) was expressed in PC12 cells and used to study the distribution, secretory behavior, and dynamics of secretory granules containing tPA in living cells with a neuronal phenotype. High-resolution images demonstrate that tPA/GFP has a growth cone-biased distribution in differentiated cells and that tPA/GFP is transported in granules of the regulated secretory pathway that colocalize with granules containing secretogranin II. Time-lapse images of secretion reveal that secretagogues induce substantial loss of cellular tPA/GFP fluorescence, most importantly from growth cones. Time-lapse images of the axonal transport of granules containing tPA/GFP reveal a surprising complexity to granule dynamics. Some granules undergo canonical fast axonal transport; others move somewhat more slowly, especially in highly fluorescent neurites. Most strikingly, granules traffic bidirectionally along neurites to an extent that depends on granule accumulation, and individual granules can reverse their direction of motion. The retrograde component of this bidirectional transport may help to maintain cellular homeostasis by transporting excess tPA/GFP back toward the cell body. The results presented here provide a novel view of the axonal transport of secretory granules. In addition, the results suggest that tPA is targeted for regulated secretion from growth cones of differentiated cells, strategically positioning tPA to degrade extracellular barriers or to activate other barrier-degrading proteases during axonal elongation.

The Dynamic Behavior of Individual Microtubules Associated with Chromosomes In Vitro

Mitotic movements of chromosomes are usually coupled to the elongation and shortening of the microtubules to which they are bound. The lengths of kinetochore-associated microtubules change by incorporation or loss of tubulin subunits, principally at their chromosome-bound ends. We have reproduced aspects of this phenomenon in vitro, using a real-time assay that displays directly the movements of individual chromosome-associated microtubules as they elongate and shorten. Chromosomes isolated from cultured Chinese hamster ovary cells were adhered to coverslips and then allowed to bind labeled microtubules. In the presence of tubulin and GTP, these microtubules could grow at their chromosome-bound ends, causing the labeled segments to move away from the chromosomes, even in the absence of ATP. Sometimes a microtubule would switch to shortening, causing the direction of movement to change abruptly. The link between a microtubule and a chromosome was mechanically strong; 15 pN of tension was generally insufficient to detach a microtubule, even though it could add subunits at the kinetochore–microtubule junction. The behavior of the microtubules in vitro was regulated by the chromosomes to which they were bound; the frequency of transitions from polymerization to depolymerization was decreased, and the speed of depolymerization-coupled movement toward chromosomes was only one-fifth the rate of shortening for microtubules free in solution. Our results are consistent with a model in which each microtubule interacts with an increasing number of chromosome-associated binding sites as it approaches the kinetochore.

How do owls localize interaurally phase-ambiguous signals?

Owls and other animals, including humans, use the difference in arrival time of sounds between the ears to determine the direction of a sound source in the horizontal plane. When an interaural time difference (ITD) is conveyed by a narrowband signal such as a tone, human beings may fail to derive the direction represented by that ITD. This is because they cannot distinguish the true ITD contained in the signal from its phase equivalents that are ITD ± nT, where T is the period of the stimulus tone and n is an integer. This uncertainty is called phase-ambiguity. All ITD-sensitive neurons in birds and mammals respond to an ITD and its phase equivalents when the ITD is contained in narrowband signals. It is not known, however, if these animals show phase-ambiguity in the localization of narrowband signals. The present work shows that barn owls (Tyto alba) experience phase-ambiguity in the localization of tones delivered by earphones. We used sound-induced head-turning responses to measure the sound-source directions perceived by two owls. In both owls, head-turning angles varied as a sinusoidal function of ITD. One owl always pointed to the direction represented by the smaller of the two ITDs, whereas a second owl always chose the direction represented by the larger ITD (i.e., ITD − T).

Origin of nanomechanical cantilever motion generated from biomolecular interactions

Generation of nanomechanical cantilever motion from biomolecular interactions can have wide applications, ranging from high-throughput biomolecular detection to bioactuation. Although it has been suggested that such motion is caused by changes in surface stress of a cantilever beam, the origin of the surface-stress change has so far not been elucidated. By using DNA hybridization experiments, we show that the origin of motion lies in the interplay between changes in configurational entropy and intermolecular energetics induced by specific biomolecular interactions. By controlling entropy change during DNA hybridization, the direction of cantilever motion can be manipulated. These thermodynamic principles were also used to explain the origin of motion generated from protein–ligand binding.

Plasticity of the cochleotopic (frequency) map in specialized and nonspecialized auditory cortices

Auditory conditioning (associative learning) causes reorganization of the cochleotopic (frequency) maps of the primary auditory cortex (AI) and the inferior colliculus. Focal electric stimulation of the AI also evokes basically the same cortical and collicular reorganization as that caused by conditioning. Therefore, part of the neural mechanism for the plasticity of the central auditory system caused by conditioning can be explored by focal electric stimulation of the AI. The reorganization is due to shifts in best frequencies (BFs) together with shifts in frequency-tuning curves of single neurons. In the AI of the Mongolian gerbil (Meriones unguiculatus) and the posterior division of the AI of the mustached bat (Pteronotus parnellii), focal electric stimulation evokes BF shifts of cortical auditory neurons located within a 0.7-mm distance along the frequency axis. The amount and direction of BF shift differ depending on the relationship in BF between stimulated and recorded neurons, and between the gerbil and mustached bat. Comparison in BF shift between different mammalian species and between different cortical areas of a single species indicates that BF shift toward the BF of electrically stimulated cortical neurons (centripetal BF shift) is common in the AI, whereas BF shift away from the BF of electrically stimulated cortical neurons (centrifugal BF shift) is special. Therefore, we propose a hypothesis that reorganization, and accordingly organization, of cortical auditory areas caused by associative learning can be quite different between specialized and nonspecialized (ordinary) areas of the auditory cortex.