Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento específicos que realizan una tarea fija durante toda su vida útil. Para cumplir con requisitos estrictos de coste, tamaño y peso, el equipo de diseño debe optimizar su funcionamiento para condiciones muy específicas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento más inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operación cada vez más dinámicos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo diseño tales como: cambios en las características de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de cómputo, por ejemplo debido a fallos o defectos de fabricación; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema dinámicos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptación autónoma sin intervención humana a lo largo de la vida útil, permitiendo que tomen sus propias decisiones en tiempo de ejecución. Éstos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras características, las de auto-configuración, auto-optimización y auto-reparación. Típicamente, la parte soft de un sistema es mayoritariamente la única utilizada para proporcionar algunas capacidades de adaptación a un sistema. Sin embargo, la proporción rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones está siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia también aumente. Además, la mejora en metodologías de diseño no ha sido acorde como para poder utilizar toda la capacidad de cómputo disponible proporcionada por los núcleos. Por todo ello, no se están satisfaciendo adecuadamente las demandas de cómputo que imponen las nuevas aplicaciones. La solución tradicional para mejorar la proporción rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producción en masa y además la naturaleza estática de su estructura complica la solución a las necesidades de adaptación. Los avances en tecnologías de fabricación han hecho que la FPGA, una vez lenta y pequeña, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de cómputo reconfigurable de gran potencia, con una cantidad enorme de recursos lógicos computacionales y cores hardware empotrados de procesamiento de señal y de propósito general. Sus capacidades de reconfiguración han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado más como estático. El motivo es que como en el caso de las FPGAs basadas en tecnología SRAM, la reconfiguración parcial dinámica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecución mientras el resto permanecen activos. Además, este proceso de reconfiguración puede ser ejecutado internamente por el propio dispositivo. El avance tecnológico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computación Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicación más exóticos y menos convencionales que ha posibilitado la computación reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a través de reconfiguración en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biológicas naturales, que guía la dirección del cambio. Es una aplicación más del campo de la Computación Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimización global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resolución de problemas. En analogía al proceso biológico de la evolución, en el hardware evolutivo el sujeto de la evolución es una población de circuitos que intenta adaptarse a su entorno mediante una adecuación progresiva generación tras generación. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuación (o fitness) después de ser evaluados, y usándolos como padres de la siguiente generación, el algoritmo evolutivo crea una nueva población hija usando operadores genéticos como la mutación y la recombinación. Según se van sucediendo generaciones, se espera que la población en conjunto se aproxime a la solución óptima al problema de encontrar una configuración del circuito adecuada que satisfaga las especificaciones. El estado de la tecnología de reconfiguración después de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obstáculo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos públicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguración lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los años 2000 permitió mantener la investigación en el campo mientras la tecnología de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que actúa como un circuito reconfigurable de aplicación específica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguración y aumenta su velocidad (comparada con la reconfiguración nativa). Es un array de nodos computacionales especificados usando descripciones HDL estándar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a través de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande actúa como memoria de configuración, por lo que la reconfiguración del VRC es muy rápida ya que tan sólo implica la escritura de este registro, el cual controla las señales de selección del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de área debido a la implementación simultánea de cada función en cada nodo del array más los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento máxima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigación sobre sistemas auto-adaptativos. Combinar un sustrato de cómputo auto-reconfigurable capaz de ser modificado dinámicamente en tiempo de ejecución con un algoritmo empotrado que proporcione una dirección de cambio, puede ayudar a satisfacer los requisitos de adaptación autónoma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis está por tanto dirigida a contribuir a la auto-adaptación del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de parámetros soft. De esta distinción, se derivan dos lineas de trabajo. Por un lado, auto-adaptación paramétrica, y por otro auto-adaptación estructural. El objetivo perseguido en el caso de la auto-adaptación paramétrica es la implementación de técnicas de optimización evolutiva complejas en sistemas empotrados con recursos limitados para la adaptación paramétrica online de circuitos de procesamiento de señal. La aplicación seleccionada como prueba de concepto es la optimización para tipos muy específicos de imágenes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresión de imágenes. Por tanto, el objetivo requerido de la evolución es una compresión adaptativa y más eficiente comparada con los procedimientos estándar. El principal reto radica en reducir la necesidad de recursos de supercomputación para el proceso de optimización propuesto en trabajos previos, de modo que se adecúe para la ejecución en sistemas empotrados. En cuanto a la auto-adaptación estructural, el objetivo de la tesis es la implementación de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguración nativas. En este caso, la prueba de concepto es la evolución de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detección de bordes en la imagen. En general, el objetivo es la evolución en tiempo de ejecución de tareas de procesamiento de imagen desconocidas en tiempo de diseño (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporación de DPR en EHW para evolucionar la arquitectura de un array sistólico adaptable mediante reconfiguración cuya capacidad de evolución no había sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptación (AE, Adaptation Engine), un motor de reconfiguración (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptación paramétrica, la plataforma propuesta está caracterizada por: • un CE caracterizado por un núcleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet • un algoritmo evolutivo como AE que busca filtros wavelet candidatos a través de un proceso de optimización paramétrica desarrollado específicamente para sistemas caracterizados por recursos de procesamiento limitados • un nuevo operador de mutación simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluación rápida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la búsqueda evolutiva asociada a la adaptación de wavelets. En el caso de adaptación estructural, la plataforma propuesta toma la forma de: • un CE basado en una plantilla de array sistólico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables • un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecución • un RE hardware que explota la capacidad de reconfiguración nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecución • una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posición, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: • Una plataforma evolutiva basada en FPGA para la auto-adaptación paramétrica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptación (AE) evolutivo y un motor de reconfiguración (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptación paramétrica y estructural. • En cuanto a la auto-adaptación paramétrica, las contribuciones principales son: – Un motor computacional adaptable mediante registros que permite la adaptación paramétrica de los coeficientes de una implementación hardware adaptativa de un núcleo de DWT. – Un motor de adaptación basado en un algoritmo evolutivo desarrollado específicamente para optimización numérica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. – Un núcleo IP de DWT auto-adaptativo en tiempo de ejecución para sistemas empotrados que permite la optimización online del rendimiento de la transformada para compresión de imágenes en entornos específicos de despliegue, caracterizados por tipos diferentes de señal de entrada. – Un modelo software y una implementación hardware de una herramienta para la construcción evolutiva automática de transformadas wavelet específicas. • Por último, en cuanto a la auto-adaptación estructural, las contribuciones principales son: – Un motor computacional adaptable mediante reconfiguración nativa de FPGAs caracterizado por una plantilla de array sistólico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de cómputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. – Definición de una biblioteca de elementos de procesamiento apropiada para la síntesis autónoma en tiempo de ejecución de diferentes tareas de procesamiento de imagen. – Incorporación eficiente de la reconfiguración parcial dinámica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo también se comparan originalmente los detalles de implementación de ambas propuestas. – Una plataforma tolerante a fallos, auto-curativa, que permite la recuperación funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguración, se hace un análisis sistemático de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. – Una plataforma con calidad de filtrado dinámica que permite la adaptación online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, también se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes dinámicamente. Este documento está organizado en cuatro partes y nueve capítulos. La primera parte contiene el capítulo 1, una introducción y motivación sobre este trabajo de tesis. A continuación, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el capítulo 2 contiene una introducción a los conceptos de auto-adaptación y computación autonómica (autonomic computing) como un campo de investigación más general que el muy específico de este trabajo; el capítulo 3 introduce la computación evolutiva como la técnica para dirigir la adaptación; el capítulo 4 analiza las plataformas de computación reconfigurables como la tecnología para albergar hardware auto-adaptativo; y finalmente, el capítulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el capítulo 6 contiene una declaración de los objetivos de la tesis y la descripción de la propuesta en su conjunto, los capítulos 7 y 8 abordan la auto-adaptación paramétrica y estructural, respectivamente. Finalmente, el capítulo 9 de la parte 4 concluye el trabajo y describe caminos de investigación futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: • a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients • an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources • a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: • a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes • an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library • a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time • a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. • An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. • Regarding parametric self-adaptation, main contributions are: – A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. – An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. – A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. – A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. • Lastly, regarding structural self-adaptation, main contributions are: – A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. – Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. – Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. – A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. – A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.

Topographical and mechanical characterization of living eukaryotic cells on opaque substrates: development of a general procedure and its application to the study of non-adherent lymphocytes

The mechanical behavior of living murine T-lymphocytes was assessed by atomic force microscopy (AFM). A robust experimental procedure was developed to overcome some features of lymphocytes, in particular their spherical shape and non-adherent character. The procedure included the immobilization of the lymphocytes on amine-functionalized substrates, the use of hydrodynamic effects on the deflection of the AFM cantilever to monitor the approaching, and the use of the jumping mode for obtaining the images. Indentation curves were analyzed according to Hertz's model for contact mechanics. The calculated values of the elastic modulus are consistent both when considering the results obtained from a single lymphocyte and when comparing the curves recorded from cells of different specimens

Mechanical behaviour and formation process of silkworm silk gut

High performance silk fibers were produced directly from the silk glands of silkworms ("Bombyx mori") following an alternative route to natural spinning. This route is based on a traditional procedure that consists of soaking the silk glands in a vinegar solution and stretching them by hand leading to the so called silkworm guts. Here we present, to the authors’ best knowledge, the first comprehensive study on the formation, properties and microstructure of silkworm gut fibers. Comparison of the tensile properties and microstructural organization of the silkworm guts with those of naturally spun fibers allows gain of a deeper insight into the mechanisms that lead to the formation of the fiber, as well as the relationship between the microstructure and properties of these materials. In this regard, it is proved that an acidic environment and subsequent application of tensile stress in the range of 1000 kPa are sufficient conditions for the formation of a silk fiber.

On the geometry of solutions of the quasi-geostrophic and Euler equations

We study solutions of the two-dimensional quasi-geostrophic thermal active scalar equation involving simple hyperbolic saddles. There is a naturally associated notion of simple hyperbolic saddle breakdown. It is proved that such breakdown cannot occur in finite time. At large time, these solutions may grow at most at a quadruple-exponential rate. Analogous results hold for the incompressible three-dimensional Euler equation.

A human fibrosarcoma inhibits systemic angiogenesis and the growth of experimental metastases via thrombospondin-1

Concomitant tumor resistance refers to the ability of some large primary tumors to hold smaller tumors in check, preventing their progressive growth. Here, we demonstrate this phenomenon with a human tumor growing in a nude mouse and show that it is caused by secretion by the tumor of the inhibitor of angiogenesis, thrombospondin-1. When growing subcutaneously, the human fibrosarcoma line HT1080 induced concomitant tumor resistance, preventing the growth of experimental B16/F10 melanoma metastases in the lung. Resistance was due to the production by the tumor cells themselves of high levels of thrombospondin-1, which was present at inhibitory levels in the plasma of tumor-bearing animals who become unable to mount an angiogenic response in their corneas. Animals carrying tumors formed by antisense-derived subclones of HT1080 that secreted low or no thrombospondin had weak or no ability to control the growth of lung metastases. Although purified human platelet thrombospondin-1 had no effect on the growth of melanoma cells in vitro, when injected into mice it was able to halt the growth of their experimental metastases, providing clear evidence of the efficacy of thrombospondin-1 as an anti-tumor agent.

Manufacturing DNA microarrays of high spot homogeneity and reduced background signal

Analyses on DNA microarrays depend considerably on spot quality and a low background signal of the glass support. By using betaine as an additive to a spotting solution made of saline sodium citrate, both the binding efficiency of spotted PCR products and the homogeneity of the DNA spots is improved significantly on aminated surfaces such as glass slides coated with the widely used poly-l-lysine or aminosilane. In addition, non-specific background signal is markedly diminished. Concomitantly, during the arraying procedure, the betaine reduces evaporation from the microtitre dish wells, which hold the PCR products. Subsequent blocking of the chip surface with succinic anhydride was improved considerably in the presence of the non-polar, non-aqueous solvent 1,2-dichloroethane and the acylating catalyst N-methylimidazole. This procedure prevents the overall background signal that occurs with the frequently applied aqueous solvent 1-methyl-2-pyrrolidone in borate buffer because of DNA that re-dissolves from spots during the blocking process, only to bind again across the entire glass surface.

Sense- and antisense-mediated gene silencing in tobacco is inhibited by the same viral suppressors and is associated with accumulation of small RNAs

Antisense-mediated gene silencing (ASGS) and posttranscriptional gene silencing (PTGS) with sense transgenes markedly reduce the steady-state mRNA levels of endogenous genes similar in transcribed sequence. RNase protection assays established that silencing in tobacco plants transformed with plant-defense-related class I sense and antisense chitinase (CHN) transgenes is at the posttranscriptional level. Infection of tobacco plants with cucumber mosaic virus strain FN and a necrotizing strain of potato virus Y, but not with potato virus X, effectively suppressed PTGS and ASGS of both the transgenes and homologous endogenes. This suggests that ASGS and PTGS share components associated with initiation and maintenance of the silent state. Small, ca. 25-nt RNAs (smRNA) of both polarities were associated with PTGS and ASGS in CHN transformants as reported for PTGS in other transgenic plants and for RNA interference in Drosophila. Similar results were obtained with an antisense class I β-1,3-glucanase transformant showing that viral suppression and smRNAs are a more general feature of ASGS. Several current models hold that diverse signals lead to production of double-stranded RNAs, which are processed to smRNAs that then trigger PTGS. Our results provide direct evidence for mechanistic links between ASGS and PTGS and suggest that ASGS could join a common PTGS pathway at the double-stranded RNA step.

Regional and cellular fractionation of working memory

This chapter recounts efforts to dissect the cellular and circuit basis of a memory system in the primate cortex with the goal of extending the insights gained from the study of normal brain organization in animal models to an understanding of human cognition and related memory disorders. Primates and humans have developed an extraordinary capacity to process information “on line,” a capacity that is widely considered to underlay comprehension, thinking, and so-called executive functions. Understanding the interactions between the major cellular constituents of cortical circuits—pyramidal and nonpyramidal cells—is considered a necessary step in unraveling the cellular mechanisms subserving working memory mechanisms and, ultimately, cognitive processes. Evidence from a variety of sources is accumulating to indicate that dopamine has a major role in regulating the excitability of the cortical circuitry upon which the working memory function of prefrontal cortex depends. Here, I describe several direct and indirect intercellular mechanisms for modulating working memory function in prefrontal cortex based on the localization of dopamine receptors on the distal dendrites and spines of pyramidal cells and on interneurons in the prefrontal cortex. Interactions between monoamines and a compromised cortical circuitry may hold the key to understanding the variety of memory disorders associated with aging and disease.

Neural mechanisms for visual memory and their role in attention

Recent studies show that neuronal mechanisms for learning and memory both dynamically modulate and permanently alter the representations of visual stimuli in the adult monkey cortex. Three commonly observed neuronal effects in memory-demanding tasks are repetition suppression, enhancement, and delay activity. In repetition suppression, repeated experience with the same visual stimulus leads to both short- and long-term suppression of neuronal responses in subpopulations of visual neurons. Enhancement works in an opposite fashion, in that neuronal responses are enhanced for objects with learned behavioral relevance. Delay activity is found in tasks in which animals are required to actively hold specific information “on-line” for short periods. Repetition suppression appears to be an intrinsic property of visual cortical areas such as inferior temporal cortex and is thought to be important for perceptual learning and priming. By contrast, enhancement and delay activity may depend on feedback to temporal cortex from prefrontal cortex and are thought to be important for working memory. All of these mnemonic effects on neuronal responses bias the competitive interactions that take place between stimulus representations in the cortex when there is more than one stimulus in the visual field. As a result, memory will often determine the winner of these competitions and, thus, will determine which stimulus is attended.

La roca magica: Uses of natural zeolites in agriculture and industry

For nearly 200 years since their discovery in 1756, geologists considered the zeolite minerals to occur as fairly large crystals in the vugs and cavities of basalts and other traprock formations. Here, they were prized by mineral collectors, but their small abundance and polymineralic nature defied commercial exploitation. As the synthetic zeolite (molecular sieve) business began to take hold in the late 1950s, huge beds of zeolite-rich sediments, formed by the alteration of volcanic ash (glass) in lake and marine waters, were discovered in the western United States and elsewhere in the world. These beds were found to contain as much as 95% of a single zeolite; they were generally flat-lying and easily mined by surface methods. The properties of these low-cost natural materials mimicked those of many of their synthetic counterparts, and considerable effort has made since that time to develop applications for them based on their unique adsorption, cation-exchange, dehydration–rehydration, and catalytic properties. Natural zeolites (i.e., those found in volcanogenic sedimentary rocks) have been and are being used as building stone, as lightweight aggregate and pozzolans in cements and concretes, as filler in paper, in the take-up of Cs and Sr from nuclear waste and fallout, as soil amendments in agronomy and horticulture, in the removal of ammonia from municipal, industrial, and agricultural waste and drinking waters, as energy exchangers in solar refrigerators, as dietary supplements in animal diets, as consumer deodorizers, in pet litters, in taking up ammonia from animal manures, and as ammonia filters in kidney-dialysis units. From their use in construction during Roman times, to their role as hydroponic (zeoponic) substrate for growing plants on space missions, to their recent success in the healing of cuts and wounds, natural zeolites are now considered to be full-fledged mineral commodities, the use of which promise to expand even more in the future.

Transgenic plants for tropical regions: Some considerations about their development and their transfer to the small farmer

Biotechnological applications, especially transgenic plants, probably hold the most promise in augmenting agricultural production in the first decades of the next millennium. However, the application of these technologies to the agriculture of tropical regions where the largest areas of low productivity are located, and where they are most needed, remains a major challenge. In this paper, some of the important issues that need to be considered to ensure that plant biotechnology is effectively transferred to the developing world are discussed.

Illite and hydrocarbon exploration

Illite is a general term for the dioctahedral mica-like clay mineral common in sedimentary rocks, especially shales. Illite is of interest to the petroleum industry because it can provide a K-Ar isotope date that constrains the timing of basin heating events. It is critical to establish that hydrocarbon formation and migration occurred after the formation of the trap (anticline, etc.) that is to hold the oil. Illite also may precipitate in the pores of sandstone reservoirs, impeding fluid flow. Illite in shales is a mixture of detrital mica and its weathering products with diagenetic illite formed by reaction with pore fluids during burial. K-Ar ages are apparent ages of mixtures of detrital and diagenetic end members, and what we need are the ages of the end members themselves. This paper describes a methodology, based on mineralogy and crystallography, for interpreting the K-Ar ages from illites in sedimentary rocks and for estimating the ages of the end members.

Pantropic retroviral vectors integrate and express in cells of the malaria mosquito, Anopheles gambiae.

The lack of efficient mechanisms for stable genetic transformation of medically important insects, such as anopheline mosquitoes, is the single most important impediment to progress in identifying novel control strategies. Currently available techniques for foreign gene expression in insect cells in culture lack the benefit of stable inheritance conferred by integration. To overcome this problem, a new class of pantropic retroviral vectors has been developed in which the amphotropic envelope is completely replaced by the G glycoprotein of vesicular stomatitis virus. The broadened host cell range of these particles allowed successful entry, integration, and expression of heterologous genes in cultured cells of Anopheles gambiae, the principle mosquito vector responsible for the transmission of over 100 million cases of malaria each year. Mosquito cells in culture infected with a pantropic vector expressing hygromycin phosphotransferase from the Drosophila hsp70 promoter were resistant to the antibiotic hygromycin B. Integrated provirus was detected in infected mosquito cell clones grown in selective media. Thus, pantropic retroviral vectors hold promise as a transformation system for mosquitoes in vivo.

Chromospheric activity and rotation of FGK stars in the solar vicinity. An estimation of the radial velocity jitter

Context. Chromospheric activity produces both photometric and spectroscopic variations that can be mistaken as planets. Large spots crossing the stellar disc can produce planet-like periodic variations in the light curve of a star. These spots clearly affect the spectral line profiles, and their perturbations alter the line centroids creating a radial velocity jitter that might “contaminate” the variations induced by a planet. Precise chromospheric activity measurements are needed to estimate the activity-induced noise that should be expected for a given star. Aims. We obtain precise chromospheric activity measurements and projected rotational velocities for nearby (d ≤ 25 pc) cool (spectral types F to K) stars, to estimate their expected activity-related jitter. As a complementary objective, we attempt to obtain relationships between fluxes in different activity indicator lines, that permit a transformation of traditional activity indicators, i.e., Ca II H & K lines, to others that hold noteworthy advantages. Methods. We used high resolution (~50 000) echelle optical spectra. Standard data reduction was performed using the IRAF ECHELLE package. To determine the chromospheric emission of the stars in the sample, we used the spectral subtraction technique. We measured the equivalent widths of the chromospheric emission lines in the subtracted spectrum and transformed them into fluxes by applying empirical equivalent width and flux relationships. Rotational velocities were determined using the cross-correlation technique. To infer activity-related radial velocity (RV) jitter, we used empirical relationships between this jitter and the R’_HK index. Results. We measured chromospheric activity, as given by different indicators throughout the optical spectra, and projected rotational velocities for 371 nearby cool stars. We have built empirical relationships among the most important chromospheric emission lines. Finally, we used the measured chromospheric activity to estimate the expected RV jitter for the active stars in the sample.

Hα emission fluxes and lithium abundances of low-mass stars in the young open cluster IC 4665

As part of a long term effort to understand pre-main sequence Li burning, we have obtained high resolution spectroscopic observations of 14 late type stars (G0-M1) in the young open cluster IC 4665. Most of the stars have Hα filled-in and Li I absorption, as expected for their young age. From the equivalent widths of Hα emission excess (obtained using the spectral subtraction technique) and the the Li i λ6708 feature, we have derived Hα emission fluxes and photospheric Li abundances. The mean Li abundance of IC 4665 solar-type stars is log N(Li) = 3.1; the same as in other young clusters (α Per, Pleiades) and T Tauri stars. Our results support the conclusions from previous works that PMS Li depletion is very small for masses ∼ 1 M_⨀ . Among the IC 4665 late-G and early K-type stars, there is a spread in Li abundances of about one order of magnitude. The Li-poor IC 4665 members have low Hα excess and vsini≤10. Hence, the Li-activity-rotation connection which has been clearly established in the Pleiades also seems to hold in IC 4665. One M-type IC 4665 star that we have observed does not show Li, implying a very efficient Li depletion as observed in α Per stars of the same spectral type. The level of chromospheric activity and Li depletion among the low-mass stars of IC 4665 is similar to that in the Pleiades. In fact, we note that the Li abundance distributions in several young clusters (α Per, Pleiades, IC 2391, IC 4665) and in post T Tauri stars are strikingly similar. This result suggests that Hα emission and Li abundance not well correlated with age for low-mass stars between 20 and 100 Myr old. We argue that a finer age indicator, the ''LL-clock'', would be the luminosity at which the transition between efficient Li depletion and preservation takes place for fully convective objects. The LL-clock could allow in the near future to derive the relative ages of young open clusters, and clarify the study of PMS evolution of cool stars.