960 resultados para Adaptive parameters


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Presentado en el 13th WSEAS International Conference on Automatic Control, Modelling and Simulation, ACMOS'11

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This paper investigates the effects of structure parameters on dynamic responses of submerged floating tunnel (SFT) under hydrodynamic loads. The structure parameters includes buoyancy-weight ratio (BWR), stiffness coefficients of the cable systems, tunnel net buoyancy and tunnel length. First, the importance of structural damp in relation to the dynamic responses of SFT is demonstrated and the mechanism of structural damp effect is discussed. Thereafter, the fundamental structure parameters are investigated through the analysis of SFT dynamic responses under hydrodynamic loads. The results indicate that the BWR of SFT is a key structure parameter. When BWR is 1.2, there is a remarkable trend change in the vertical dynamic response of SFT under hydrodynamic loads. The results also indicate that the ratio of the tunnel net buoyancy to the cable stiffness coefficient is not a characteristic factor affecting the dynamic responses of SFT under hydrodynamic loads.

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A quadtree-based adaptive Cartesian grid generator and flow solver were developed. The grid adaptation based on pressure or density gradient was performed and a gridless method based on the least-square fashion was used to treat the wall surface boundary condition, which is generally difficult to be handled for the common Cartesian grid. First, to validate the technique of grid adaptation, the benchmarks over a forward-facing step and double Mach reflection were computed. Second, the flows over the NACA 0012 airfoil and a two-element airfoil were calculated to validate the developed gridless method. The computational results indicate the developed method is reasonable for complex flows.

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This study examines zooplankton periodicity and some physicochemical parameters of the intake channel of Lake Chad (Nigeria). Nine different zooplankton species were identified at the sampling station 1, while seven different zooplankton species were identified at the sampling station 2 (the intake channel of Lake Chad). Each identified zooplankton species was grouped according to its major group of copepods, Cladocera or Rotifera. The copepods dominated the zooplankton community with the highest numbers of occurrence as Cyclopedia species throughout the course of the study at both station l and 2. There was a clear evidence of the influence of organic manure nutrients on total zooplankton population at station 1 when compared to that of station 2. The water quality variables measured in the course of this study show that the surface water temperature in station 1 ranges from 27.5 degree C to 30.5 degree C. The pH ranges from 6.8 to 8.5, while D.O. contents ranges from 2.9mg/L to 6.1mg/L and alkalinity recorded was 172.00 to 208.00. At the station 2 the water quality parameters obtained show that surface water temperature ranges from 27.3 degree C to 30.2 degree C, pH ranges between 6.9 to 8.5, while the D.O contents ranges from 3.0 mg/L to 6.2 mg/L.Alkalinity ranges from 172mg/L to 212 mg/L

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Singular Value Decomposition (SVD) is a key linear algebraic operation in many scientific and engineering applications. In particular, many computational intelligence systems rely on machine learning methods involving high dimensionality datasets that have to be fast processed for real-time adaptability. In this paper we describe a practical FPGA (Field Programmable Gate Array) implementation of a SVD processor for accelerating the solution of large LSE problems. The design approach has been comprehensive, from the algorithmic refinement to the numerical analysis to the customization for an efficient hardware realization. The processing scheme rests on an adaptive vector rotation evaluator for error regularization that enhances convergence speed with no penalty on the solution accuracy. The proposed architecture, which follows a data transfer scheme, is scalable and based on the interconnection of simple rotations units, which allows for a trade-off between occupied area and processing acceleration in the final implementation. This permits the SVD processor to be implemented both on low-cost and highend FPGAs, according to the final application requirements.