LMP triggered real time demand response events

Recent changes in power systems mainly due to the substantial increase of distributed generation and to the operation in competitive environments has created new challenges to operation and planning. In this context, Virtual Power Players (VPP) can aggregate a diversity of players, namely generators and consumers, and a diversity of energy resources, including electricity generation based on several technologies, storage and demand response. Demand response market implementation has been done in recent years. Several implementation models have been considered. An important characteristic of a demand response program is the trigger criterion. A program for which the event trigger depends on the Locational Marginal Price (LMP) used by the New England Independent System operator (ISO-NE) inspired the present paper. This paper proposes a methodology to support VPP demand response programs management. The proposed method has been computationally implemented and its application is illustrated using a 32 bus network with intensive use of distributed generation. Results concerning the evaluation of the impact of using demand response events are also presented.

Power systems reliability calculation based on fuzzy data mining

This paper presents a methodology supported on the data base knowledge discovery process (KDD), in order to find out the failure probability of electrical equipments’, which belong to a real electrical high voltage network. Data Mining (DM) techniques are used to discover a set of outcome failure probability and, therefore, to extract knowledge concerning to the unavailability of the electrical equipments such us power transformers and high-voltages power lines. The framework includes several steps, following the analysis of the real data base, the pre-processing data, the application of DM algorithms, and finally, the interpretation of the discovered knowledge. To validate the proposed methodology, a case study which includes real databases is used. This data have a heavy uncertainty due to climate conditions for this reason it was used fuzzy logic to determine the set of the electrical components failure probabilities in order to reestablish the service. The results reflect an interesting potential of this approach and encourage further research on the topic.

Análise do padrão motor em pessoas com diagnóstico de esquizofrenia: uma abordagem em tempo real

A esquizofrenia é uma perturbação mental grave caracterizada pela coexistência de sintomas positivos, negativos e de desorganização do pensamento e do comportamento. As alterações motoras são consistentemente observadas mas, ainda pouco estudadas na esquizofrenia, sendo relevantes para o seu diagnóstico. Neste quadro, o presente estudo tem como objetivo verificar se os indivíduos com esquizofrenia apresentam alterações na coordenação motora, comparativamente com o grupo sem esquizofrenia, bem como analisar se as disfunções dos sinais neurológicos subtis (SNS) motores se encontram correlacionadas com o funcionamento executivo e com os domínios psicopatológicos da perturbação. No total participaram 29 indivíduos (13 com diagnóstico de esquizofrenia e 16 sem diagnóstico) equivalentes em termos de idade, género, escolaridade e índice de massa corporal. Para avaliar o desempenho motor recorreu-se ao sistema Biostage de parametrização do movimento em tempo real, com a tarefa de lançameto ao alvo; a presença de SNS foi examinada através da Brief Motor Scale; o funcionamento executivo pela aplicação do subteste do Vocabulário e da fluência verbal e a sintomatologia clínica através da Positive and Negative Sindrome Scale. Pela análise cinemática do movimento constatou-se que os indivíduos com esquizofrenia recrutam um padrão motor menos desenvolvido e imaturo de movimento, com menor individualização das componentes (principalmente do tronco e pélvis), necessitando de mais tempo para executar a tarefa, comparativamente com os sujeitos sem a perturbação que evidenciaram um movimento mais avançado de movimento. Os indivíduos com esquizofrenia mostraram índices elevados de disfunção dos SNS (média =6,01) estabelecendo este domínio uma relação boa e negativa com o desempenho verbal (rho Spearman=-0,62) e uma relação forte e positiva com todos os domínios psicopatológicos (rho Spearman=0,74). O estudo da existência de alterações motoras como parte intrínseca da esquizofrenia revela-se pertinente uma vez que possibilita uma compreensão mais aprofundada da sua fisiopatologia e permite que se desenvolvam práticas mais efetivas na área da saúde e reabilitação.

Chlormequat selective electrodes: construction, evaluation and application at FIA systems

A flow injection analysis (FIA) system having a chlormequat selective electrode is proposed. Several electrodes with poly(vinyl chloride) based membranes were constructed for this purpose. Comparative characterization suggestedthe use of membrane with chlormequat tetraphenylborate and dibutylphthalate. On a single-line FIA set-up, operating with 1x10-2 mol L-1 ionic strength and 6.3 pH, calibration curves presented slopes of 53.6±0.4mV decade-1 within 5.0x10-6 and1.0x10-3 mol L-1, andsquaredcorrelation coefficients >0.9953. The detection limit was 2.2x10-6 mol L-1 and the repeatability equal to ±0.68mV (0.7%). A dual-channel FIA manifold was therefore constructed, enabling automatic attainment of previous ionic strength andpH conditions and thus eliminating sample preparation steps. Slopes of 45.5±0.2mV decade -1 along a concentration range of 8.0x10-6 to 1.0x10-3 mol L-1 with a repeatability ±0.4mV (0.69%) were obtained. Analyses of real samples were performed, and recovery gave results ranging from 96.6 to 101.1%.

Assigning real-time tasks on heterogeneous multiprocessors with two unrelated types of processors

A preliminary version of this paper appeared in Proceedings of the 31st IEEE Real-Time Systems Symposium, 2010, pp. 239–248.

Distributed computing for the factory-floor: a real-time approach using WorldFIP networks

Field communication systems (fieldbuses) are widely used as the communication support for distributed computer-controlled systems (DCCS) within all sort of process control and manufacturing applications. There are several advantages in the use of fieldbuses as a replacement for the traditional point-to-point links between sensors/actuators and computer-based control systems, within which the most relevant is the decentralisation and distribution of the processing power over the field. A widely used fieldbus is the WorldFIP, which is normalised as European standard EN 50170. Using WorldFIP to support DCCS, an important issue is “how to guarantee the timing requirements of the real-time traffic?” WorldFIP has very interesting mechanisms to schedule data transfers, since it explicitly distinguishes periodic and aperiodic traffic. In this paper, we describe how WorldFIP handles these two types of traffic, and more importantly, we provide a comprehensive analysis on how to guarantee the timing requirements of the real-time traffic.

Software transactional memory as a building block for parallel embedded realtime systems

The recent trends of chip architectures with higher number of heterogeneous cores, and non-uniform memory/non-coherent caches, brings renewed attention to the use of Software Transactional Memory (STM) as a fundamental building block for developing parallel applications. Nevertheless, although STM promises to ease concurrent and parallel software development, it relies on the possibility of aborting conflicting transactions to maintain data consistency, which impacts on the responsiveness and timing guarantees required by embedded real-time systems. In these systems, contention delays must be (efficiently) limited so that the response times of tasks executing transactions are upper-bounded and task sets can be feasibly scheduled. In this paper we assess the use of STM in the development of embedded real-time software, defending that the amount of contention can be reduced if read-only transactions access recent consistent data snapshots, progressing in a wait-free manner. We show how the required number of versions of a shared object can be calculated for a set of tasks. We also outline an algorithm to manage conflicts between update transactions that prevents starvation.

EMMON: a WSN system architecture for large scale and dense real-time embedded monitoring

Wireless sensor networks (WSNs) have attracted growing interest in the last decade as an infrastructure to support a diversity of ubiquitous computing and cyber-physical systems. However, most research work has focused on protocols or on specific applications. As a result, there remains a clear lack of effective, feasible and usable system architectures that address both functional and non-functional requirements in an integrated fashion. In this paper, we outline the EMMON system architecture for large-scale, dense, real-time embedded monitoring. EMMON provides a hierarchical communication architecture together with integrated middleware and command and control software. It has been designed to use standard commercially-available technologies, while maintaining as much flexibility as possible to meet specific applications requirements. The EMMON architecture has been validated through extensive simulation and experimental evaluation, including a 300+ node test-bed, which is, to the best of our knowledge, the largest single-site WSN test-bed in Europe to date.

Towards real multi-criticality scheduling

Componentised systems, in particular those with fault confinement through address spaces, are currently emerging as a hot topic in embedded systems research. This paper extends the unified rate-based scheduling framework RBED in several dimensions to fit the requirements of such systems: we have removed the requirement that the deadline of a task is equal to its period. The introduction of inter-process communication reflects the need to communicate. Additionally we also discuss server tasks, budget replenishment and the low level details needed to deal with the physical reality of systems. While a number of these issues have been studied in previous work in isolation, we focus on the problems discovered and lessons learned when integrating solutions. We report on our experiences implementing the proposed mechanisms in a commercial grade OKL4 microkernel as well as an application with soft real-time and best-effort tasks on top of it.

A compositional scheduling framework for digital avionics systems

ARINC specification 653-2 describes the interface between application software and underlying middleware in a distributed real-time avionics system. The real-time workload in this system comprises of partitions, where each partition consists of one or more processes. Processes incur blocking and preemption overheads and can communicate with other processes in the system. In this work we develop compositional techniques for automated scheduling of such partitions and processes. At present, system designers manually schedule partitions based on interactions they have with the partition vendors. This approach is not only time consuming, but can also result in under utilization of resources. In contrast, the technique proposed in this paper is a principled approach for scheduling ARINC-653 partitions and therefore should facilitate system integration.

Scheduling arbitrary-deadline sporadic task systems on multiprocessors

A new algorithm is proposed for scheduling preemptible arbitrary-deadline sporadic task systems upon multiprocessor platforms, with interprocessor migration permitted. This algorithm is based on a task-splitting approach - while most tasks are entirely assigned to specific processors, a few tasks (fewer than the number of processors) may be split across two processors. This algorithm can be used for two distinct purposes: for actually scheduling specific sporadic task systems, and for feasibility analysis. Simulation- based evaluation indicates that this algorithm offers a significant improvement on the ability to schedule arbitrary- deadline sporadic task systems as compared to the contemporary state-of-art. With regard to feasibility analysis, the new algorithm is proved to offer superior performance guarantees in comparison to prior feasibility tests.

Real-time communications over cluster-tree sensor networks with mobile sink behaviour

Modelling the fundamental performance limits of wireless sensor networks (WSNs) is of paramount importance to understand the behaviour of WSN under worst case conditions and to make the appropriate design choices. In that direction, this paper contributes with a methodology for modelling cluster tree WSNs with a mobile sink. We propose closed form recurrent expressions for computing the worst case end to end delays, buffering and bandwidth requirements across any source-destination path in the cluster tree assuming error free channel. We show how to apply our theoretical results to the specific case of IEEE 802.15.4/ZigBee WSNs. Finally, we demonstrate the validity and analyze the accuracy of our methodology through a comprehensive experimental study, therefore validating the theoretical results through experimentation.

Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.