907 resultados para Dynamic Input-Output Balance
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This work presents simulations of the Electrofluid Dynamic energy conversion process in slender channel devices having very small particles (in both micro and nano scales) as charge carriers. Solutions are discussed for a system composed by coupled differential equations, which includes the equation for the total current along the channel, the equations for total energy and momentum of the mixture (gas and solid particles), the continuity equation and the equations for energy and momentum of a single particle. Results for suspended particles of higher diameters have been previously published in the Literature, but the simulations here presented exhibit an appreciable increase in the values for output currents.
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This work presents simulations of the Electrofluid Dynamic energy conversion process in slender channel devices having very small particles (in both micro and nano scales) as charge carriers. Solutions are discussed for a system composed by coupled differential equations, which includes the equation for the total current along the channel, the equations for total energy and momentum of the mixture (gas and solid particles), the continuity equation and the equations for energy and momentum of a single particle. Results for suspended particles of higher diameters have been previously published in the Literature, but the simulations here presented exhibit an appreciable increase in the values for output currents.
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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
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A linear, tunable CMOS transconductance stage is introduced. Drain voltage of the input transistor operating in triode region is settled by a regulation loop and a first-order linear relationship between g(m) and a de bias voltage is achieved. In addition to easy tuning, this technique offers circuit simplicity, wide dynamic range, high input and output impedances and low consumption. The transconductor is presented on both single-ended and fully-differential versions. A 3rd-order elliptical low-pass g(m)-C filter with a nominal roll-off frequency of 2MHz is used as one example for the many applications of the proposed transconductor. SPICE data describe circuits performances and filter tunabilily Passband is tuned at a rate of 2.36KHz/mV and good linearity is indicated by a 0.89% THD for an 800mV(p-p) balanced-driven input.
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A CMOS low-voltage, wide-swing continuous-time current amplifier is presented. Exhibiting an open-loop architecture, the circuit is composed of transresistance and transconductance stages built upon triode-operating transistors. In addition to an extended dynamic range, the current gain can be programmed within good accuracy by a rapport involving only transistor geometries and tuning biases. Low temperature-drift on gain setting is then expected.In accordance with a 0.35 mum n-well CMOS fabrication process and a single 1.1 V-supply, a balanced current-amplifier is designed for a programmable gain-range of 6 - 34 dB and optimized with respect to dynamic range. Simulated results from PSPICE and Bsim3v3 models indicate, for a 100 muA(pp)-output current, a THD of 0.96 and 1.87% at 1 KHz and 100 KHz, respectively. Input noise is 120 pArootHz @ 10 Hz, with S/N = 63.2 dB @ 1%-THD. At maximum gain, total quiescent consumption is 334 muW. Measurements from a prototyped amplifier reveal a gain-interval of 4.8-33.1 dB and a maximum current swing of 120 muA(pp). The current-amplifier bandwidth is above 1 MHz.
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A robust 12 kW rectifier with low THD in the line currents, based on an 18-pulse transformer arrangement with reduced kVA capacities followed by a high-frequency isolation stage is presented in this work. Three full-bridge (buck-based) converters are used to allow galvanic isolation and to balance the dc-link currents, without current sensing or current controller. The topology provides a regulated dc output with a very simple and well-known control strategy and natural three-phase power factor correction. The phase-shift PWM technique, with zero-voltage switching is used for the high-frequency dc-dc stage. Analytical results from Fourier analysis of winding currents and the vector diagram of winding voltages are presented. Experimental results from a 12 kW prototype are shown in the paper to verify the efficiency, robustness and simplicity of the command circuitry to the proposed concept.
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This paper deals with the design and analysis of a Dynamic Voltage Restorer output voltage control. Such control is based on a multiloop strategy, with an inner current PID regulator and an outer P+Resonant voltage controller. The inner regulator is applied on the output inductor current. It will be also demonstrated how the load current behavior may influence in the DVR output voltage, which. justifies the need for the resonant controller. Additionally, it will be discussed the application of a modified algorithm for the identification of the DVR voltage references, which is based on a previously presented positive sequence detector. Since the studied three-phase DVR is assumed to be based on three identical H-bridge converters, all the analysis and design procedures were realized by means of single-phase equivalent circuits. The discussions and conclusions are supported by theoretical calculations, nonlinear simulations and some experimental results.
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A linearly tunable low-voltage CMOS transconductor featuring a new adaptative-bias mechanism that considerably improves the stability of the processed-signal common,mode voltage over the tuning range, critical for very-low voltage applications, is introduced. It embeds a feedback loop that holds input devices on triode region while boosting the output resistance. Analysis of the integrator frequency response gives an insight into the location of secondary poles and zeros as function of design parameters. A third-order low-pass Cauer filter employing the proposed transconductor was designed and integrated on a 0.8-mum n-well CMOS standard process. For a 1.8-V supply, filter characterization revealed f(p) = 0.93 MHz, f(s) = 1.82 MHz, A(min) = 44.08, dB, and A(max) = 0.64 dB at nominal tuning. Mined by a de voltage V-TUNE, the filter bandwidth was linearly adjusted at a rate of 11.48 kHz/mV over nearly one frequency decade. A maximum 13-mV deviation on the common-mode voltage at the filter output was measured over the interval 25 mV less than or equal to V-TUNE less than or equal to 200 mV. For V-out = 300 mV(pp) and V-TUNE = 100 mV, THD was -55.4 dB. Noise spectral density was 0.84 muV/Hz(1/2) @1 kHz and S/N = 41 dB @ V-out = 300 mV(pp) and 1-MHz bandwidth. Idle power consumption was 1.73 mW @V-TUNE = 100 mV. A tradeoff between dynamic range, bandwidth, power consumption, and chip area has then been achieved.
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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
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Although conventional rotating machines have been largely used to drive underground transportation systems, linear induction motors are also being considered for future applications owing to their indisputable advantages. A mathematical model for the transient behavior analysis of linear induction motors, when operating with constant r.m.s. currents, is presented in this paper. Operating conditions, like phase short-circuit and input frequency variations and also some design characteristics, such as air-gap and secondary resistivity variations, can be considered by means of this modeling. The basis of the mathematical modeling is presented. Experimental results obtained in the laboratory are compared with the corresponding simulations and discussed in this paper.
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This work presents a new high power factor three-phase rectifier based on a Y-connected differential autotransformer with reduced kVA and 18-pulse input current followed by three DC-DC boost converters. The topology provides a regulated output voltage and natural three-phase input power factor correction. The lowest input current harmonic components are the 17th and the 19th. Three boost converters, with constant input currents and regulated parallel connected output voltages are used to process 4kW each one. Analytical results from Fourier analyses of winding currents and the vector diagram of winding voltages are presented. Simulation results to verify the proposed concept and experimental results are shown in the paper.
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A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.
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This work proposes a new isolated high power factor 12kW power supply based on an 18-pulse transformer arrangement. Three full-bridge converters are used for isolation and to balance the DC-link currents, without current sensing or a current controller. The topology provides a regulated DC output with a very simple control strategy. Simulation and experimental results are presented in this paper.
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Piezoelectric actuators are widely used in positioning systems which demand high resolution such as scanning microscopy, fast mirror scanners, vibration cancellation, cell manipulation, etc. In this work a piezoelectric flextensional actuator (PFA), designed with the topology optimization method, is experimentally characterized by the measurement of its nanometric displacements using a Michelson interferometer. Because this detection process is non-linear, adequate techniques must be applied to obtain a linear relationship between an output electrical signal and the induced optical phase shift. Ideally, the bias phase shift in the interferometer should remain constant, but in practice it suffers from fading. The J1-J4 spectral analysis method provides a linear and direct measurement of dynamic phase shift in a no-feedback and no-phase bias optical homodyne interferometer. PFA application such as micromanipulation in biotechnology demands fast and precise movements. So, in order to operate with arbitrary control signals the PFA must have frequency bandwidth of several kHz. However as the natural frequencies of the PFA are low, unwanted dynamics of the structure are often a problem, especially for scanning motion, but also if trajectories have to be followed with high velocities, because of the tracking error phenomenon. So the PFA must be designed in such a manner that the first mechanical resonance occurs far beyond this band. Thus it is important to know all the PFA resonance frequencies. In this work the linearity and frequency response of the PFA are evaluated up to 50 kHz using optical interferometry and the J1-J4 method.