A molecular dynamics study of the influence of chain branching on the properties of polymer systems

Die vorliegende Arbeit beschäftigt sich mit dem Einfluß von Kettenverzweigungen unterschiedlicher Topologien auf die statischen Eigenschaften von Polymeren. Diese Untersuchungen werden mit Hilfe von Monte-Carlo- und Molekular-Dynamik-Simulationen durchgeführt.Zunächst werden einige theoretische Konzepte und Modelle eingeführt, welche die Beschreibung von Polymerketten auf mesoskopischen Längenskalen gestatten. Es werden wichtige Bestimmungsgrößen eingeführt und erläutert, welche zur quantitativen Charakterisierung von Verzweigungsstrukturen bei Polymeren geeignet sind. Es wird ebenso auf die verwendeten Optimierungstechniken eingegangen, die bei der Implementierung des Computerprogrammes Verwendung fanden. Untersucht werden neben linearen Polymerketten unterschiedliche Topolgien -Sternpolymere mit variabler Armzahl, Übergang von Sternpolymeren zu linearen Polymeren, Ketten mit variabler Zahl von Seitenketten, reguläre Dendrimere und hyperverzweigte Strukturen - in Abhängigkeit von der Lösungsmittelqualität. Es wird zunächst eine gründliche Analyse des verwendeten Simulationsmodells an sehr langen linearen Einzelketten vorgenommen. Die Skalierungseigenschaften der linearen Ketten werden untersucht in dem gesamten Lösungsmittelbereich vom guten Lösungsmittel bis hin zu weitgehend kollabierten Ketten im schlechten Lösungsmittel. Ein wichtiges Ergebnis dieser Arbeit ist die Bestätigung der Korrekturen zum Skalenverhalten des hydrodynamischen Radius Rh. Dieses Ergebnis war möglich aufgrund der großen gewählten Kettenlängen und der hohen Qualität der erhaltenen Daten in dieser Arbeit, insbesondere bei den linearen ketten, und es steht im Widerspruch zu vielen bisherigen Simulations-Studien und experimentellen Arbeiten. Diese Korrekturen zum Skalenverhalten wurden nicht nur für die linearen Ketten, sondern auch für Sternpolymere mit unterchiedlicher Armzahl gezeigt. Für lineare Ketten wird der Einfluß von Polydispersität untersucht.Es wird gezeigt, daß eine eindeutige Abbildung von Längenskalen zwischen Simulationsmodell und Experiment nicht möglich ist, da die zu diesem Zweck verwendete dimensionslose Größe eine zu schwache Abhängigkeit von der Polymerisation der Ketten besitzt. Ein Vergleich von Simulationsdaten mit industriellem Low-Density-Polyäthylen(LDPE) zeigt, daß LDPE in Form von stark verzweigten Ketten vorliegt.Für reguläre Dendrimere konnte ein hochgradiges Zurückfalten der Arme in die innere Kernregion nachgewiesen werden.

Nonlinear Control Strategies for Cooperative Control of Multi-Robot Systems

This thesis deals with distributed control strategies for cooperative control of multi-robot systems. Specifically, distributed coordination strategies are presented for groups of mobile robots. The formation control problem is initially solved exploiting artificial potential fields. The purpose of the presented formation control algorithm is to drive a group of mobile robots to create a completely arbitrarily shaped formation. Robots are initially controlled to create a regular polygon formation. A bijective coordinate transformation is then exploited to extend the scope of this strategy, to obtain arbitrarily shaped formations. For this purpose, artificial potential fields are specifically designed, and robots are driven to follow their negative gradient. Artificial potential fields are then subsequently exploited to solve the coordinated path tracking problem, thus making the robots autonomously spread along predefined paths, and move along them in a coordinated way. Formation control problem is then solved exploiting a consensus based approach. Specifically, weighted graphs are used both to define the desired formation, and to implement collision avoidance. As expected for consensus based algorithms, this control strategy is experimentally shown to be robust to the presence of communication delays. The global connectivity maintenance issue is then considered. Specifically, an estimation procedure is introduced to allow each agent to compute its own estimate of the algebraic connectivity of the communication graph, in a distributed manner. This estimate is then exploited to develop a gradient based control strategy that ensures that the communication graph remains connected, as the system evolves. The proposed control strategy is developed initially for single-integrator kinematic agents, and is then extended to Lagrangian dynamical systems.

Questionnaire-based study to assess the association between management practices and mastitis within tie-stall and free-stall dairy housing systems in Switzerland.

BACKGROUND Prophylactic measures are key components of dairy herd mastitis control programs, but some are only relevant in specific housing systems. To assess the association between management practices and mastitis incidence, data collected in 2011 by a survey among 979 randomly selected Swiss dairy farms, and information from the regular test day recordings from 680 of these farms was analyzed. RESULTS The median incidence of farmer-reported clinical mastitis (ICM) was 11.6 (mean 14.7) cases per 100 cows per year. The median annual proportion of milk samples with a composite somatic cell count (PSCC) above 200,000 cells/ml was 16.1 (mean 17.3) %. A multivariable negative binomial regression model was fitted for each of the mastitis indicators for farms with tie-stall and free-stall housing systems separately to study the effect of other (than housing system) management practices on the ICM and PSCC events (above 200,000 cells/ml). The results differed substantially by housing system and outcome. In tie-stall systems, clinical mastitis incidence was mainly affected by region (mountainous production zone; incidence rate ratio (IRR) = 0.73), the dairy herd replacement system (1.27) and farmers age (0.81). The proportion of high SCC was mainly associated with dry cow udder controls (IRR = 0.67), clean bedding material at calving (IRR = 1.72), using total merit values to select bulls (IRR = 1.57) and body condition scoring (IRR = 0.74). In free-stall systems, the IRR for clinical mastitis was mainly associated with stall climate/temperature (IRR = 1.65), comfort mats as resting surface (IRR = 0.75) and when no feed analysis was carried out (IRR = 1.18). The proportion of high SSC was only associated with hand and arm cleaning after calving (IRR = 0.81) and beef producing value to select bulls (IRR = 0.66). CONCLUSIONS There were substantial differences in identified risk factors in the four models. Some of the factors were in agreement with the reported literature while others were not. This highlights the multifactorial nature of the disease and the differences in the risks for both mastitis manifestations. Attempting to understand these multifactorial associations for mastitis within larger management groups continues to play an important role in mastitis control programs.

A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self- Adaptive Systems

Modern FPGAs with Dynamic and Partial Reconfiguration (DPR) feature allow the implementation of complex, yet flexible, hardware systems. Combining this flexibility with evolvable hardware techniques, real adaptive systems, able to reconfigure themselves according to environmental changes, can be envisaged. In this paper, a highly regular and modular architecture combined with a fast reconfiguration mechanism is proposed, allowing the introduction of dynamic and partial reconfiguration in the evolvable hardware loop. Results and use case show that, following this approach, evolvable processing IP Cores can be built, providing intensive data processing capabilities, improving data and delay overheads with respect to previous proposals. Results also show that, in the worst case (maximum mutation rate), average reconfiguration time is 5 times lower than evaluation time.

Soil fragmentation study applying different tillage systems

Runoff generation depends on rainfall, infiltration, interception, and surface depressional storage. Surface depressional storage depends on surface microtopography, usually quantified trough soil surface roughness (SSR). SSR is subject to spatial and temporal changes that create a high variability. In an agricultural environment, tillage operations produce abrupt changes in roughness. Subsequent rainfall gradually decreases roughness. Beside it, local variation in soil properties and hydrology cause its SSR to vary spatially at different scales. The methods commonly used to measure it involve collecting point elevations in regular grids using laser profilers or scanners, digital close range stereo-photogrammetry and terrestrial laser scanning or LIDAR systems. In this case, a laser-scanning instrument was used to obtain representative digital elevation models (DEMs) at a grid resolution of 7.2x7.2mm that cover an area of 0.9x0.9m. The DEMs were obtained from two study sites with different soils. The first study site was an experimental field on which five conventional tillage methods were applied. The second study site was a large olive orchard with trees planted at 7.5x5.0m and bare soils between rows. Here, three tillage treatments were applied. In this work we have evaluated the spatial variability of SSR at several scales studying differences in height calculated from points separated by incremental distances h were raised to power values q (from 0 to 4 in steps of 0.1). The q = 2 data were studied as a semivariogram model. The logarithm of average differences plotted vs. log h were characterized by their slope, ?(q). Structure functions [?(q) vs. q] were fitted showing that data had nonlinear structure functions typical of multiscale phenomena. Comparisson of the two types of soil in their respective structure functions are shown.

Accepting splicing systems with permitting and forbidding words

Abstract: In this paper we propose a generalization of the accepting splicingsystems introduced in Mitrana et al. (Theor Comput Sci 411:2414?2422,2010). More precisely, the input word is accepted as soon as a permittingword is obtained provided that no forbidding word has been obtained sofar, otherwise it is rejected. Note that in the new variant of acceptingsplicing system the input word is rejected if either no permitting word isever generated (like in Mitrana et al. in Theor Comput Sci 411:2414?2422,2010) or a forbidding word has been generated and no permitting wordhad been generated before. We investigate the computational power ofthe new variants of accepting splicing systems and the interrelationshipsamong them. We show that the new condition strictly increases thecomputational power of accepting splicing systems. Although there areregular languages that cannot be accepted by any of the splicing systemsconsidered here, the new variants can accept non-regular and even non-context-free languages, a situation that is not very common in the case of(extended) finite splicing systems without additional restrictions. We alsoshow that the smallest class of languages out of the four classes definedby accepting splicing systems is strictly included in the class of context-free languages. Solutions to a few decidability problems are immediatelyderived from the proof of this result.

Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems

Dynamically Reconfigurable Systems are attracting a growing interest, mainly due to the emergence of novel applications based on this technology. However, commercial tools do not provide enough flexibility to design solutions, while keeping an acceptable design productivity. In this paper, a novel design flow is proposed, targeting dynamically reconfigurable systems. It is fully supported by a tool called Dreams, which is able to implement flexible systems, starting from a set of netlists corresponding to the modules, as well as a system description provided by the user. The tool automatically post-processes the nets, implementing a solution for the communications between reconfigurable regions, as well as the handling of routing conflicts, by means of a custom router. Since the design process of every module and the static system are independent, the proposed flow is compatible with system upgrade at run-time. In this paper, a use case corresponding to the design of a highly regular and parallel mesh-type architecture is described, in order to show the architectural flexibility offered by the tool.

Splicing Systems: Accepting Versus Generating.

In this paper we propose a condition for rejecting the input word by an accepting splicing system which is defined by a finite set of forbidding words. We investigate the computational power of the new variants of accepting splicing systems. We show that the new condition strictly increases the computational power of accepting splicing systems. Rather surprisingly, accepting splicing systems considered here can accept non-regular languages, a situation that has never occurred in the case of (extended) finite splicing systems without additional restrictions.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

Optimal polygonal L1 linearization and fast interpolation of nonlinear systems

The analysis of complex nonlinear systems is often carried out using simpler piecewise linear representations of them. A principled and practical technique is proposed to linearize and evaluate arbitrary continuous nonlinear functions using polygonal (continuous piecewise linear) models under the L1 norm. A thorough error analysis is developed to guide an optimal design of two kinds of polygonal approximations in the asymptotic case of a large budget of evaluation subintervals N. The method allows the user to obtain the level of linearization (N) for a target approximation error and vice versa. It is suitable for, but not limited to, an efficient implementation in modern Graphics Processing Units (GPUs), allowing real-time performance of computationally demanding applications. The quality and efficiency of the technique has been measured in detail on two nonlinear functions that are widely used in many areas of scientific computing and are expensive to evaluate.

New systems of management to improve the health and welfare of rabbits in farm conditions = Nuevos sistemas de cría y manejo para mejorar la salud y bienestar de conejos de granja

El objetivo general de esta Tesis Doctoral fue evaluar nuevos sistemas de alojamiento y cría de conejos de granja, estudiando tanto parámetros comportamentales (experimento 1) como productivos y reproductivos (experimento 3). Además, se evaluaron diferentes técnicas de muestreo con el fin de optimizar el tiempo empleado para el estudio del comportamiento animal (experimento 2). En el experimento 1, se estudió el comportamiento de conejas alojadas en dos tipos de jaulas (TJ), convencionales vs. alternativas con una plataforma elevada, en distintos estados fisiológicos (EF), lactantes y gestantes. Se observó el comportamiento de 12 conejas reproductoras con grabaciones de una duración de 24 h continuas. Independientemente del EF y TJ, las conejas pasaron gran parte de su tiempo sobre el reposapatas (57,7 %, de media). Sin embargo, debido al uso de la plataforma (23,0% del tiempo, de media), las conejas lactantes permanecieron un 36,6 % menos de tiempo (P<0,001) sobre el reposapatas y las gestantes un 27,0% menos (P<0,001) sobre el enrejillado en jaulas alternativas que en convencionales. En las jaulas alternativas, las conejas podían adoptar la postura “levantada”, sin embargo ésta fue observada solamente en conejas gestantes una media de 4,6 veces al día. Las conejas bebieron con mas frecuencia en jaulas convencionales que en alternativas (24,6 vs 19,1 veces al día; P<0,05). Se observó una mayor duración y frecuencia del comportamiento “interactuando con compañeras” en conejas gestantes alojadas en jaulas convencionales (276 s/d y 4,6 veces/d; P<0,05). La frecuencia de “interactuando con gazapos” fue menor en jaulas alternativas que en convencionales (2,4 vs 8,6 veces al día; P<0,01). La hora del día afectó al comportamiento de las conejas, teniendo un comportamiento menos activo durante las horas centrales del día. Durante las horas de oscuridad, las conejas estuvieron más inquietas realizando comportamientos como ‘encabritarse’ o amamantar, coincidiendo éstos en el tiempo en el cual las conejas pasaron más tiempo en la plataforma. Las conejas utilizaron frecuentemente la plataforma, independientemente del estado fisiológico. En la fase de lactación, las conejas utilizaron la plataforma para huir de los intentos de mamar por parte de los gazapos cuando éstas no estaban receptivas. El uso de la plataforma puede dar lugar a problemas higiénicos debidos tanto por la acumulación de heces sobre ella como por la caída de heces y orina sobre los animales que están en la parte inferior. La ausencia de estereotipias por parte de las conejas tanto en jaulas alternativas como en convencionales no sugiere una falta de bienestar debida al sistema de alojamiento. En el experimento 2, se compararon distintos métodos de observación simplificada con respecto un método de referencia usando grabaciones continuas de 24 h para la evaluación del comportamiento de conejas en distintos estados fisiológicos (gestantes y lactantes) alojadas en dos tipos de jaulas (convencionales y alternativas). Se analizaron un total de 576 h de grabaciones continuas de 24 h en 12 conejas reproductoras al final del periodo de lactación y en las mismas conejas después del destete. Los comportamientos observados se clasificaron en tres categorías independientes (localización en la jaula, postura y comportamientos funcionales). Se utilizaron grabaciones continuas de 24 h como método de referencia para validar otros cuatro métodos de observación simplificados, utilizando grabaciones de distinta duración y frecuencia a lo largo del día. Métodos regulares: corto y largo con 2.4 y 8 h de observación respectivamente, y métodos irregulares: corto y largo con 6 y 8 h de observación, respectivamente. Como resultado, se observó que independientemente del sistema de alojamiento, el mejor método para reducir el tiempo de observación necesario para evaluar el comportamiento de conejas reproductoras depende del tipo de variable a estudiar y del estado fisiológico de las conejas. En gestantes, los métodos irregulares no fueron adecuados para estimar comportamientos de larga duración tales como tumbada, sentada, descansando y acicalándose. Sin embargo, en ambos estados fisiológicos, los métodos regulares fueron precisos para los comportamientos de los grupos localización y postura y para comportamientos funcionales de larga duración. Por otro lado, los coeficientes de variación de los comportamientos poco frecuentes realizados principalmente durante el periodo de oscuridad fueron muy altos, y el método irregular largo obtuvo los menores errores de estimación para éstos comportamientos. En el experimento 3, se estudió el efecto de un uso combinado de lactaciones largas (hasta 46 días) con jaulas alternativas sobre los parámetros productivos y reproductivos de 104 conejas y sus camadas durante cinco ciclos reproductivos. La mitad de las conejas fueron alojadas en jaulas polivalentes convencionales (39 cm x 100 cm x 30 cm) y la otra mitad en jaulas polivalentes alternativas (39 cm x 100 cm x 60 cm), con una plataforma elevada. Dentro de cada grupo de alojamiento, la mitad de las conejas se destetaron a 32 días y la otra mitad a 46 días tras el parto. Las lactaciones más largas afectaron negativamente al peso (P<0,001), contenido en grasa y energía (P<0,05) de las conejas al final del periodo de lactación, pero éste efecto disminuyó con el número de partos. La fertilidad, prolificidad y la mortalidad de las conejas no fue afectada por la duración de la lactación. El destete tardío dio lugar a un mayor tamaño y peso de la camada al final del periodo de crecimiento (8,9 y 11,3 %, respectivamente) y a un menor índice de conversión por jaula durante el todo el periodo experimental (13,5 %) con respecto al destete convencional (P<0,001). Éstos resultados fueron paralelos a la menor mortalidad global (12,6 vs 17,6 %; P<0,05) observada en gazapos con destete tardío. Las diferencias en los parámetros productivos con las distintas edades al destete sólo fueron observadas en los ciclos con peor estado sanitario (tercer y quinto ciclo), en los cuales el destete tardío redujo la mortalidad. El tipo de jaula no afectó al peso de la coneja, condición corporal, mortalidad, fertilidad ni tamaño de camada durante los cinco primeros ciclos reproductivos. Sin embargo, el peso de la camada y el índice de conversión a los 21 días de edad fueron 4,2% mayor (P<0,001) y 5,0% menor (P<0,005) en animales alojados en jaulas alternativas que en jaulas convencionales. A día 59 las jaulas alternativas dieron lugar a camadas más pesadas (P<0,01); sin embargo, éste efecto fue influenciado por la densidad alcanzada en cada ciclo, ya que cuando la densidad de los animales fue menor que 40kg/m2 (tercer y quinto ciclo), el efecto del tipo de jaula sobre el peso de la camada no fue significativo. De los resultados obtenidos se puede concluir que el uso combinado de lactaciones más largas y jaulas con mayor superficie disponible con una plataforma elevada podría ser una alternativa para mejorar el bienestar animal en determinadas situaciones productivas. ABSTRACT The general aim of this PhD Thesis was to evaluate new housing and husbandry systems of farmed rabbits, studying behavioral (experiment 1), productive and reproductive (experiment 3) parameters. Moreover, different sampling techniques were evaluated in order to optimize the assessment of rabbit behaviour (experiment 2). In experiment 1, the behaviour of rabbit does housed in two different types of cage (TC), conventional vs. alternative with an elevated platform, at different physiological stages (PS), lactation and gestation was to study. Behavioural observations were carried out on 12 commercial rabbit does using continuous 24 hour video recording. Independently of PS and TC, rabbit does spent most of their time on foot mats (57.7 %, as average). However, due to the use of platforms (23.0% of time, as average), lactating does spent 36.6% less time (P<0.001) on foot mats and gestating does spent 27.0% less (P<0.001) time on wire mesh in alternative cages than in conventional cages. Alternative cages allowed for standing posture but this behaviour was only observed in gestating does (4.6 times a day, as average). Frequency of drinking was higher in conventional than in alternative cages (24.6 vs. 19.1 times a day; P<0.05). Gestating does housed in conventional cages reached the highest duration and frequency of interacting with neighbours (276 s/d and 4.6 times/d; P<0.05). The frequency of interacting with kits was lower in alternative than in conventional cages (2.4 vs. 8.6 times a day; P<0.01). Does’ behaviour was influenced by hour of day, being less active at the midday hours. During dark hours rabbit does more frequently performed restless behaviour such as hyperactivity or nursing, matching the time at which rabbit does spent more time on the platform. The platform was frequently used by rabbit does, independent of their physiological state, and during late lactation phase, when mothers were not receptive to nursing, does housed in alternative cages used the platform as a mean to flee from kids trying to suckle. The use of the platform might lead to hygienic problems due to retained faeces on the platform and faeces and urine falling onto animals located in the lower part of the cage. Stereotypies were not observed in any housing system, therefore conventional cages do not suggest lack of animal welfare. In experiment 2, it was compared the results of different simplified sampling methods of behavioural data with respect to reference records of 24-h in order to assess rabbit does behaviours at different physiological stages (gestation and lactation) in animals housed in two types of cages (conventional and alternative). A total of 576 h of continuous video of 12 rabbit does at the end of lactation and on the same females after weaning were analysed. The behavioural observations were studied using three independent categories of classification (location in the cage, posture and functional behaviours). Continuous behavioural recordings of 24 h were considered as the reference method to validate another 4 sampling methods of data collection by aggregated video recordings of different frequency and duration (regular short and long methods with 2.4 and 8 h of observation respectively, and irregular short and long methods with 6 and 8 h of observation, respectively). The current results showed that, independently of housing system, the best method to reduce the total observation time required to assess rabbit does behaviour depends on the trait studied and physiological stage of does. In gestating does, irregular methods were not suitable to estimate behaviours of long duration such as lying, sitting, resting and grooming. However, in both physiological stages, regular methods were accurate for location behaviours, postures and functional behaviours of long duration. Instead, for the study of infrequent behaviours performed mainly during dark period, where coefficients of variation were high, the irregular long method led to the lowest mean estimation errors. In experiment 3, the effects of the combined use of long lactation periods (46 days) with alternative cages on the reproductive and growth performance of 104 rabbit does and their litters during five consecutive reproductive cycles were studied. Half of does were housed in conventional polyvalent cages (39 cm x 100 cm x 30 cm) and the other half in alternative polyvalent cages (39 cm x 100 cm x 60 cm), with a raised platform. Half of the rabbit does in each type of cages were weaned at 32 and the other half at 46 days after parturition. Longer lactations affected negatively to body weight (P<0.001), fat and energy content (P<0.05) of rabbit does at the end of the lactation period, but this effect decreased with the number of parturitions. Fertility, prolificacy and doe mortality were not affected by lactation length. Late weaning led to higher litter size (by 8.9 %) and litter weight (by 11.3 %) at the end of growing period and lower feed conversion ratio per cage during the overall experimental period (13.5 %) than standard weaning (P<0.001). These results were parallels to a lower mortality (12.6 vs 17.6 %; P<0.05) of young rabbit weaned later during the overall experimental period. Differences in performances at different weaning ages were only observed during cycles with worst health status (third and fifth cycles) in which late weaning decreased mortality. Type of cage did not affect doe body weight and body condition, mortality, fertility, prolificacy and litter size during the five firsts reproductive cycles. Nevertheless, at day 21 litter weight and feed conversion ratio were 4.2 % higher (P<0.001) and 5.0 % lower (P<0.005) in animals housed in alternative than in conventional cages. Alternative cages also led to heavier litters at 59 days (P<0.01); however, this effect was influenced by density reached in each cycle, as when the density of animals was lower than 40 kg/m2 (cycles three and five), the difference of litter weight between alternative and conventional cages was not significant. From the results obtained it can be concluded that the combined use of longer lactations and cages with higher available surface with a raised platform could be an alternative to improve animal welfare in some productive situations.

The relationship between non-orthographic language abilities and reading performance: An exploration of the primary systems hypothesis in chronic aphasia

Thesis (Ph.D.)--University of Washington, 2016-06

Alcohol use and risk taking among regular ecstasy users

We examine alcohol use in conjunction with ecstasy use and risk-taking behaviors among regular ecstasy users in every capital city in Australia. Data on drug use and risks were collected in 2004 from a national sample of 852 regular ecstasy users (persons who had used ecstasy at least monthly in the preceding 6 months). Users were grouped according to their typical alcohol use when using ecstasy: no use, consumption of between one and five standard drinks, and consumption of more than five drinks (binge alcohol use). The sample was young, well educated, and mainly working or studying. Approximately two thirds (65%) of the regular ecstasy users reported drinking alcohol when taking ecstasy. Of these, 69% reported usually consuming more than five standard drinks. Those who did not drink alcohol were more disadvantaged, with greater levels of unemployment, less education, higher rates of drug user treatment, and prison history. They were also more likely than those who drank alcohol when using ecstasy to be drug injectors and to be hepatitis C positive. Excluding alcohol, drug use patterns were similar between groups, although the no alcohol group used cannabis and methamphetamine more frequently. Binge drinkers were more likely to report having had three or more sexual partners in the past 6 months and were less likely to report having safe sex with casual partners while under the influence of drugs. Despite some evidence that the no alcohol group were more entrenched drug users, those who typically drank alcohol when taking ecstasy were as likely to report risks and problems associated with their drug use. It appears that regular ecstasy users who binge drink are placing themselves at increased sexual risk when under the influence of drugs. Safe sex messages should address the sexual risk associated with substance use and should be tailored to reducing alcohol consumption, particularly targeting heavy alcohol users. The study's limitations are noted.

A statistical-mechanical analysis of coded CDMA with regular LDPC codes

We analyze, using the replica method of statistical mechanics, the theoretical performance of coded code-division multiple-access (CDMA) systems in which regular low-density parity-check (LDPC) codes are used for channel coding.