Tecniche per il controllo dinamico del consumo di potenza per piattaforme system-on-chip

Providing support for multimedia applications on low-power mobile devices remains a significant research challenge. This is primarily due to two reasons: • Portable mobile devices have modest sizes and weights, and therefore inadequate resources, low CPU processing power, reduced display capabilities, limited memory and battery lifetimes as compared to desktop and laptop systems. • On the other hand, multimedia applications tend to have distinctive QoS and processing requirementswhichmake themextremely resource-demanding. This innate conflict introduces key research challenges in the design of multimedia applications and device-level power optimization. Energy efficiency in this kind of platforms can be achieved only via a synergistic hardware and software approach. In fact, while System-on-Chips are more and more programmable thus providing functional flexibility, hardwareonly power reduction techniques cannot maintain consumption under acceptable bounds. It is well understood both in research and industry that system configuration andmanagement cannot be controlled efficiently only relying on low-level firmware and hardware drivers. In fact, at this level there is lack of information about user application activity and consequently about the impact of power management decision on QoS. Even though operating system support and integration is a requirement for effective performance and energy management, more effective and QoSsensitive power management is possible if power awareness and hardware configuration control strategies are tightly integratedwith domain-specificmiddleware services. The main objective of this PhD research has been the exploration and the integration of amiddleware-centric energymanagement with applications and operating-system. We choose to focus on the CPU-memory and the video subsystems, since they are the most power-hungry components of an embedded system. A second main objective has been the definition and implementation of software facilities (like toolkits, API, and run-time engines) in order to improve programmability and performance efficiency of such platforms. Enhancing energy efficiency and programmability ofmodernMulti-Processor System-on-Chips (MPSoCs) Consumer applications are characterized by tight time-to-market constraints and extreme cost sensitivity. The software that runs on modern embedded systems must be high performance, real time, and even more important low power. Although much progress has been made on these problems, much remains to be done. Multi-processor System-on-Chip (MPSoC) are increasingly popular platforms for high performance embedded applications. This leads to interesting challenges in software development since efficient software development is a major issue for MPSoc designers. An important step in deploying applications on multiprocessors is to allocate and schedule concurrent tasks to the processing and communication resources of the platform. The problem of allocating and scheduling precedenceconstrained tasks on processors in a distributed real-time system is NP-hard. There is a clear need for deployment technology that addresses thesemulti processing issues. This problem can be tackled by means of specific middleware which takes care of allocating and scheduling tasks on the different processing elements and which tries also to optimize the power consumption of the entire multiprocessor platform. This dissertation is an attempt to develop insight into efficient, flexible and optimalmethods for allocating and scheduling concurrent applications tomultiprocessor architectures. It is a well-known problem in literature: this kind of optimization problems are very complex even in much simplified variants, therefore most authors propose simplified models and heuristic approaches to solve it in reasonable time. Model simplification is often achieved by abstracting away platform implementation ”details”. As a result, optimization problems become more tractable, even reaching polynomial time complexity. Unfortunately, this approach creates an abstraction gap between the optimization model and the real HW-SW platform. The main issue with heuristic or, more in general, with incomplete search is that they introduce an optimality gap of unknown size. They provide very limited or no information on the distance between the best computed solution and the optimal one. The goal of this work is to address both abstraction and optimality gaps, formulating accurate models which accounts for a number of ”non-idealities” in real-life hardware platforms, developing novel mapping algorithms that deterministically find optimal solutions, and implementing software infrastructures required by developers to deploy applications for the targetMPSoC platforms. Energy Efficient LCDBacklightAutoregulation on Real-LifeMultimediaAp- plication Processor Despite the ever increasing advances in Liquid Crystal Display’s (LCD) technology, their power consumption is still one of the major limitations to the battery life of mobile appliances such as smart phones, portable media players, gaming and navigation devices. There is a clear trend towards the increase of LCD size to exploit the multimedia capabilities of portable devices that can receive and render high definition video and pictures. Multimedia applications running on these devices require LCD screen sizes of 2.2 to 3.5 inches andmore to display video sequences and pictures with the required quality. LCD power consumption is dependent on the backlight and pixel matrix driving circuits and is typically proportional to the panel area. As a result, the contribution is also likely to be considerable in future mobile appliances. To address this issue, companies are proposing low power technologies suitable for mobile applications supporting low power states and image control techniques. On the research side, several power saving schemes and algorithms can be found in literature. Some of them exploit software-only techniques to change the image content to reduce the power associated with the crystal polarization, some others are aimed at decreasing the backlight level while compensating the luminance reduction by compensating the user perceived quality degradation using pixel-by-pixel image processing algorithms. The major limitation of these techniques is that they rely on the CPU to perform pixel-based manipulations and their impact on CPU utilization and power consumption has not been assessed. This PhDdissertation shows an alternative approach that exploits in a smart and efficient way the hardware image processing unit almost integrated in every current multimedia application processors to implement a hardware assisted image compensation that allows dynamic scaling of the backlight with a negligible impact on QoS. The proposed approach overcomes CPU-intensive techniques by saving system power without requiring either a dedicated display technology or hardware modification. Thesis Overview The remainder of the thesis is organized as follows. The first part is focused on enhancing energy efficiency and programmability of modern Multi-Processor System-on-Chips (MPSoCs). Chapter 2 gives an overview about architectural trends in embedded systems, illustrating the principal features of new technologies and the key challenges still open. Chapter 3 presents a QoS-driven methodology for optimal allocation and frequency selection for MPSoCs. The methodology is based on functional simulation and full system power estimation. Chapter 4 targets allocation and scheduling of pipelined stream-oriented applications on top of distributed memory architectures with messaging support. We tackled the complexity of the problem by means of decomposition and no-good generation, and prove the increased computational efficiency of this approach with respect to traditional ones. Chapter 5 presents a cooperative framework to solve the allocation, scheduling and voltage/frequency selection problem to optimality for energyefficient MPSoCs, while in Chapter 6 applications with conditional task graph are taken into account. Finally Chapter 7 proposes a complete framework, called Cellflow, to help programmers in efficient software implementation on a real architecture, the Cell Broadband Engine processor. The second part is focused on energy efficient software techniques for LCD displays. Chapter 8 gives an overview about portable device display technologies, illustrating the principal features of LCD video systems and the key challenges still open. Chapter 9 shows several energy efficient software techniques present in literature, while Chapter 10 illustrates in details our method for saving significant power in an LCD panel. Finally, conclusions are drawn, reporting the main research contributions that have been discussed throughout this dissertation.

Die Regulation der Ubiquitinligase CHIP durch das Cochaperon BAG2 im zellulären System und im Kontext der replikativen Seneszenz

Eine funktionierende Proteinqualitätskontrolle ist essenziell für die Vitalität einer Zelle. Das dynamische Gleichgewicht zwischen Proteinfaltung und -degradation wird von molekularen Chaperonen aufrechterhalten, deren Aktivität wiederum durch die Interaktion mit zahlreichen Cochaperonen moduliert wird. Das Cochaperon CHIP ist ein zentraler Faktor in Proteintriage-Entscheidungsprozessen, da es als Ubiquitinligase Chaperonsubstrate dem Abbau zuführt und somit die Chaperonmaschinerie direkt mit den Systemen der Proteindegradation verbindet. Um Polypeptide vor einem vorzeitigen Abbau zu schützen, wird die destruktive Aktivität von CHIP durch weitere Cochaperone reguliert. rnIn dieser Arbeit konnte die Hemmung der Ligaseaktivität von CHIP durch das Cochaperon BAG2 mechanistisch erstmals in einem zellulären System nachgewiesen werden. Dazu wurde die humane IMR-90 Fibroblasten Zelllinie verwendet. Die Ubiquitinierungsaktivität von CHIP wurde anhand von HSP72 als Modell-CHIP-Substrat untersucht. Durch die verringerte Ubiquitinierung, und damit dem reduzierten Abbau von HSP72, regulierte BAG2 dessen intrazelluläre Proteinspiegel, ohne dabei selbst eine Hitzeschockantwort zu induzieren. Überexprimiertes BAG2 wirkte sich trotz stabilisierter HSP72-Spiegel bei einem appliziertem Hitzestresses negativ auf die Zellvitalität aus, vermutlich da BAG2 durch die Inhibition von CHIP-vermittelter Ubiquitinierung massiv in das Gleichgewicht zwischen Substratfaltung und -degradation eingreift.rnDa sich die Mechanismen der Proteinqualitätskontrolle in der Alterung stark verändern und sich den wandelnden Bedingungen in der Zelle anpassen, wurde in einem zweiten Teil dieser Arbeit mit Hilfe des IMR-90 Zellsystems als etabliertes Modell zellulärer Seneszenz analysiert, inwieweit sich die Aktivität und die Regulation von CHIP durch BAG2 in der zellulären Alterung ändern. In seneszenten Zellen war HSP72 erheblich weniger ubiquitiniert als in jungen Fibroblasten, was auf eine reduzierte CHIP-Aktivität hinweist. Diese blieb jedoch durch BAG2 weiterhin modulierbar. Die Funktion von BAG2 als Inhibitor der Ubiquitinligase CHIP blieb demnach in seneszenten Zellen bestehen. In gealterten Fibroblasten regulierte BAG2 außerdem die Proteinspiegel des CHIP-Substrates und Seneszenzinitiators p53, was BAG2 eine mögliche Rolle in der Etablierung des Seneszenz-Phänotyps zuspricht. Weiterhin unterlagen die Proteinspiegel der beiden funktionell redundanten CHIP-Modulatoren BAG2 und HSPBP1 in der zellulären Alterung einer reziproken Regulation. In gealterten Mäusen trat die gegenläufige Veränderung der beiden Cochaperone gewebsspezifisch in der Lunge auf. Außerdem waren die BAG2-Proteinspiegel im Hippocampus gealterter Tiere signifikant erhöht.rnZusammenfassend konnte anhand der erzielten Ergebnisse die Funktion von BAG2 als Inhibitor von CHIP im zellulären System bestätigt werden. Außerdem durchlaufen die Aktivität und die Regulation von CHIP einen seneszenzspezifischen Adaptationsprozess, welcher für die Erhaltung der Proteostase in der Alterung relevant sein könnte und in welchem die Funktion von BAG2 als CHIP-Modulator möglicherweise eine wichtige Rolle spielt.rnZukünftige Studien könnten die komplexen Mechanismen weiterführend aufklären, mit denen CHIP-Aktivität reguliert wird. Dies kann helfen, der altersbedingten Abnahme an proteostatischer Kontrolle entgegenzuwirken und aberrante Proteinaggregation in altersassoziierten Erkrankungen vorzubeugen.rn

Microfluidic wound-healing assay to assess the regenerative effect of HGF on wounded alveolar epithelium

We present a microfluidic epithelial wound-healing assay that allows characterization of the effect of hepatocyte growth factor (HGF) on the regeneration of alveolar epithelium using a flow-focusing technique to create a regular wound in the epithelial monolayer. The phenotype of the epithelial cell was characterized using immunostaining for tight junction (TJ) proteins and transmission electron micrographs (TEMs) of cells cultured in the microfluidic system, a technique that is reported here for the first time. We demonstrate that alveolar epithelial cells cultured in a microfluidic environment preserve their phenotype before and after wounding. In addition, we report a wound-healing benefit induced by addition of HGF to the cell culture medium (19.2 vs. 13.5 μm h(-1) healing rate).

Desarrollo de aplicaciones basadas en Linux Embedded en una arquitectura basada en Cyclone V SoC (System on Chip) de Altera

We attempt to integrate and start up the set of necessary tools to deploy the design cycle of embedded systems based on Embedded Linux on a "Cyclone V SoC" made by Altera. First, we will analyze the available tools for designing the hardware system of the SoCkit development kit, made by Arrow, which has a "Cyclone V SoC" system (based on a "ARM Cortex-A9 MP Core" architecture). When designing the SoCkit board hardware, we will create a new peripheral to integrate it into the hardware system, so it can be used as any other existent resource of the SoCkit board previously configured. Next, we will analyze the tools to generate an Embedded Linux distribution adapted to the SoCkit board. In order to generate the Linux distribution we will use, on the one hand, a software package from Yocto recommended by Altera; on the other hand, the programs and tools of Altera, Embedded Development Suite. We will integrate all the components needed to build the Embedded Linux distribution, creating a complete and functional system which can be used for developing software applications. Finally, we will study the programs for developing and debugging applications in C or C++ language that will be executed in this hardware platform, then we will program a Linux application as an example to illustrate the use of SoCkit board resources. RESUMEN Se pretende integrar y poner en funcionamiento el conjunto de herramientas necesarias para desplegar el ciclo de diseño de sistemas embebidos basados en "Embedded Linux" sobre una "Cyclone V SoC" de Altera. En primer lugar, se analizarán las diversas herramientas disponibles para diseñar el sistema hardware de la tarjeta de desarrollo SoCkit, fabricada por Arrow, que dispone de un sistema "Cyclone V SoC" (basado en una arquitectura "ARM Cortex A9 MP Core"). En el diseño hardware de la SoCkit se creará un periférico propio y se integrará en el sistema, pudiendo ser utilizado como cualquier otro recurso de la tarjeta ya existente y configurado. A continuación, también se analizarán las herramientas para generar una distribución de "Embedded Linux" adaptado a la placa SoCkit. Para generar la distribución de Linux se utilizará, por una parte, un paquete software de Yocto recomendado por Altera y, por otra parte, las propias herramientas y programas de Altera. Se integrarán todos los componentes necesarios para construir la distribución Linux, creando un sistema completo y funcional que se pueda utilizar para el desarrollo de aplicaciones software. Por último, se estudiarán las herramientas para el diseño y depuración de aplicaciones en lenguaje C ó C++ que se ejecutarán en esta plataforma hardware. Se pretende desarrollar una aplicación de ejemplo para ilustrar el uso de los recursos más utilizados de la SoCkit.

A real-time asymmetric multiprocessor-reconfigurable system-on-chip architecture

We propose an asymmetric multi-processor SoC architecture, featuring a master CPU running uClinux, and multiple loosely-coupled slave CPUs running real-time threads assigned by the master CPU. Real-time SoC architectures often demand a compromise between a generic platform for different applications, and application-specific customizations to achieve performance requirements. Our proposed architecture offers a generic platform running a conventional embedded operating system providing a traditional software-oriented development approach, while multiple slave CPUs act as a dedicated independent real-time threads execution unit running in parallel of master CPU to achieve performance requirements. In this paper, the architecture is described, including the application / threading development environment. The performance of the architecture with several standard benchmark routines is also analysed.