Direct evaluation of IEC 61850-9-2 process bus network performance

This letter presents a technique to assess the overall network performance of sampled value process buses based on IEC 61850-9-2 using measurements from a single location in the network. The method is based upon the use of Ethernet cards with externally synchronized time stamping, and characteristics of the process bus protocol. The application and utility of the method is demonstrated by measuring latency introduced by Ethernet switches. Network latency can be measured from a single set of captures, rather than comparing source and destination captures. Absolute latency measures will greatly assist the design testing, commissioning and maintenance of these critical data networks.

Melt electrospinning of poly(epsilon-caprolactone) scaffolds: Phenomenological observations associated with collection and direct writing

Melt electrospinning and its additive manufacturing analogue, melt electrospinning writing (MEW), are two processes which can produce porous materials for applications where solvent toxicity and accumulation in solution electrospinning are problematic. This study explores the melt electrospinning of poly(ε-caprolactone) (PCL) scaffolds, specifically for applications in tissue engineering. The research described here aims to inform researchers interested in melt electrospinning about technical aspects of the process. This includes rapid fiber characterization using glass microscope slides, allowing influential processing parameters on fiber morphology to be assessed, as well as observed fiber collection phenomena on different collector substrates. The distribution and alignment of melt electrospun PCL fibers can be controlled to a certain degree using patterned collectors to create large numbers of scaffolds with shaped macroporous architectures. However, the buildup of residual charge in the collected fibers limits the achievable thickness of the porous template through such scaffolds. One challenge identified for MEW is the ability to control charge buildup so that fibers can be placed accurately in close proximity, and in many centimeter heights. The scale and size of scaffolds produced using MEW, however, indicate that this emerging process will fill a technological niche in biofabrication.

The UPAL process: a direct method of preparing cast aluminium alloy-graphite particle composites

A direct method of preparing cast aluminium alloy-graphite particle composites using uncoated graphite particles is reported. The method consists of introducing and dispersing uncoated but suitably pretreated graphite particles in aluminium alloy melts, and casting the resulting composite melts in suitable permanent moulds. The optical pretreatment required for the dispersion of the uncoated graphite particles in aluminium alloy melts consists of heating the graphite particles to 400° C in air for 1 h just prior to their dispersion in the melts. The effects of alloying elements such as Si, Cu and Mg on the dispersability of pretreated graphite in molten aluminium have also been reported. It was found that additions of about 0.5% Mg or 5% Si significantly improve the dispersability of graphite particles in aluminium alloy melts as indicated by the high recoveries of graphite in the castings of these composites. It was also possible to disperse upto 3% graphite in LM 13 alloy melts and retain the graphite particles in a well distributed fashion in the castings using the pre-heat-treated graphite particles. The observations in this study have been related to the information presently available on wetting between graphite and molten aluminium in the presence of different elements and our own thermogravimetric analysis studies on graphite particles. Physical and mechanical properties of LM 13-3% graphite composite made using pre-heat-treated graphite powder, were found to be adequate for many applications, including pistons which have been successfully used in internal combustion engines.

One step self-aligned multilayer patterning process for the fabrication of organic complementary circuits in combination with inkjet printing

Recent development of solution processable organic semiconductors delineates the emergence of a new generation of air-stable, high performance p- and n-type materials. This makes it indeed possible for printed organic complementary circuits (CMOS) to be used in real applications. The main technical bottleneck for organic CMOS to be adopted as the next generation organic integrated circuit is how to deposit and pattern both p- and n-type semiconductor materials with high resolutions at the same time. It represents a significant technical challenge, especially if it can be done for multiple layers without mask alignment. In this paper, we propose a one-step self-aligned fabrication process which allows the deposition and high resolution patterning of functional layers for both p- and n-channel thin film transistors (TFTs) simultaneously. All the dimensional information of the device components is featured on a single imprinting stamp, and the TFT-channel geometry, electrodes with different work functions, p- and n-type semiconductors and effective gate dimensions can all be accurately defined by one-step imprinting and the subsequent pattern transfer process. As an example, we have demonstrated an organic complementary inverter fabricated by 3D imprinting in combination with inkjet printing and the measured electrical characteristics have validated the feasibility of the novel technique. © 2012 Elsevier B.V. All rights reserved.

Direct visualization of collapse process of porphyrin monolayers and porphyrin exclusion for mixed monolayers at the air-water interface

The collapse process of porphyrin monolayers at the air-water interface was studied by Brewster angle microscopy and by compression-recompression isotherms. It was found that the start of collapse observed by BAM is accordant with that measured by compression-recompression isotherms. The behavior of mixed monolayers was studied also and the results showed that porphyrin islands were excluded from mixed monolayers at 35mN/m.

Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process

This paper presents the results of a packaging process based on the stencil printing of isotropic conductive adhesives (ICAs) that form the interconnections of flip-chip bonded electronic packages. Ultra-fine pitch (sub-100-mum), low temperature (100degC), and low cost flip-chip assembly is demonstrated. The article details recent advances in electroformed stencil manufacturing that use microengineering techniques to enable stencil fabrication at apertures sizes down to 20mum and pitches as small as 30mum. The current state of the art for stencil printing of ICAs and solder paste is limited between 150-mum and 200-mum pitch. The ICAs-based interconnects considered in this article have been stencil printed successfully down to 50-mum pitch with consistent printing demonstrated at 90-mum pitch size. The structural integrity or the stencil after framing and printing is also investigated through experimentation and computational modeling. The assembly of a flip-chip package based on copper column bumped die and ICA deposits stencil printed at sub-100-mum pitch is described. Computational fluid dynamics modeling of the print performance provides an indicator on the optimum print parameters. Finally, an organic light emitting diode display chip is packaged using this assembly process