945 resultados para circuits and Systems


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Prefacio de Alicia Bárcena y Luciano Sáez

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A generic bio-inspired adaptive architecture for image compression suitable to be implemented in embedded systems is presented. The architecture allows the system to be tuned during its calibration phase. An evolutionary algorithm is responsible of making the system evolve towards the required performance. A prototype has been implemented in a Xilinx Virtex-5 FPGA featuring an adaptive wavelet transform core directed at improving image compression for specific types of images. An Evolution Strategy has been chosen as the search algorithm and its typical genetic operators adapted to allow for a hardware friendly implementation. HW/SW partitioning issues are also considered after a high level description of the algorithm is profiled which validates the proposed resource allocation in the device fabric. To check the robustness of the system and its adaptation capabilities, different types of images have been selected as validation patterns. A direct application of such a system is its deployment in an unknown environment during design time, letting the calibration phase adjust the system parameters so that it performs efcient image compression. Also, this prototype implementation may serve as an accelerator for the automatic design of evolved transform coefficients which are later on synthesized and implemented in a non-adaptive system in the final implementation device, whether it is a HW or SW based computing device. The architecture has been built in a modular way so that it can be easily extended to adapt other types of image processing cores. Details on this pluggable component point of view are also given in the paper.

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Modern FPGAs with run-time reconfiguration allow the implementation of complex systems offering both the flexibility of software-based solutions combined with the performance of hardware. This combination of characteristics, together with the development of new specific methodologies, make feasible to reach new points of the system design space, and make embedded systems built on these platforms acquire more and more importance. However, the practical exploitation of this technique in fields that traditionally have relied on resource restricted embedded systems, is mainly limited by strict power consumption requirements, the cost and the high dependence of DPR techniques with the specific features of the device technology underneath. In this work, we tackle the previously reported problems, designing a reconfigurable platform based on the low-cost and low-power consuming Spartan-6 FPGA family. The full process to develop the platform will be detailed in the paper from scratch. In addition, the implementation of the reconfiguration mechanism, including two profiles, is reported. The first profile is a low-area and low-speed reconfiguration engine based mainly on software functions running on the embedded processor, while the other one is a hardware version of the same engine, implemented in the FPGA logic. This reconfiguration hardware block has been originally designed to the Virtex-5 family, and its porting process will be also described in this work, facing the interoperability problem among different families.

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In this paper, the results of six years of research in engineering education, in the application of the European Higher Education Area (EHEA) to improve the performance of the students in the subject Analysis of Circuits of Telecommunication Engineering, are analysed taking into consideration the fact that there would be hidden variables that both separate students into subgroups and show the connection among several basic subjects such as Analysis of Circuits (AC) and Mathematics (Math). The discovery of these variables would help us to explain the characteristics of the students through the teaching and learning methodology, and would show that there are some characteristics that instructors do not take into account but that are of paramount importance

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The tremendous expansion and the differentiation of the neocortex constitute two major events in the evolution of the mammalian brain. The increase in size and complexity of our brains opened the way to a spectacular development of cognitive and mental skills. This expansion during evolution facilitated the addition of microcircuits with a similar basic structure, which increased the complexity of the human brain and contributed to its uniqueness. However, fundamental differences even exist between distinct mammalian species. Here, we shall discuss the issue of our humanity from a neurobiological and historical perspective.

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This work introduces the lines of research that the NGCPV project is pursuing and some of the first results obtained. Sponsored by the European Commission under the 7th Framework Program and NEDO (Japan) within the first collaborative call launched by both Bodies in the field of energy, NGCPV project aims at approaching the cost of the photovoltaic kWh to competitive prices in the framework of high concentration photovoltaics (CPV) by exploring the development and assessment of concentrator photovoltaic solar cells and modules, novel materials and new solar cell structures as well as methods and procedures to standardize measurement technology for concentrator photovoltaic cells and modules. More specific objectives we are facing are: (1) to manufacture a cell prototype with an efficiency of at least 45% and to undertake an experimental activity, (2) to manufacture a 35% module prototype and elaborate the roadmap towards the achievement of 40%, (3) to develop reliable characterization techniques for III-V materials and quantum structures, (4) to achieve and agreement within 5% in the characterization of CPV cells and modules in a round robin scheme, and (5) to evaluate the potential of new materials, devices technologies and quantum nanostructures to improve the efficiency of solar cells for CPV.

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Variabilities associated with CMOS evolution affect the yield and performance of current digital designs. FPGAs, which are widely used for fast prototyping and implementation of digital circuits, also suffer from these issues. Proactive approaches start to appear to achieve self-awareness and dynamic adaptation of these devices. To support these techniques we propose the employment of a multi-purpose sensor network. This infrastructure, through adequate use of configuration and automation tools, is able to obtain relevant data along the life cycle of an FPGA. This is realised at a very reduced cost, not only in terms of area or other limited resources, but also regarding the design effort required to define and deploy the measuring infrastructure. Our proposal has been validated by measuring inter-die and intra-die variability in different FPGA families.

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Higher education students demand fast feedback about their assignments and the opportunity to repeat them in case they do in a wrong way. Here a computer based trainer for Signals and Systems students is presented. An application, that automatically generates and assesses thousands of numerically different versions of several Signals and Systems problems have been developed. This applet guides the students to find the solution and automatically assesses and grades the students proposed solution. The students can use the application to practice in solving several types of Signals and Systems basic problems. After selecting the problem type, the student introduces a seed and the application generates a numerical version of the selected problem. Then the application presents a sequence of questions that the students must solve and the application automatically assess their answers. After solving a given problem, the students can repeat the same numerical variation of the problem by introducing the same seed to the application. In this way, they can review their solution with the help of the hints given by the application for wrong solutions. This application can also be used as an automatic assessment tool by the instructor. When the assessment is made in a controlled environment (examination classroom or laboratory) the instructor can use the same seed for all students. Otherwise, different seeds can be assigned to different students and in this way they solve different numerical variation of the proposed problem, so cheating becomes an arduous task. Given a problem type, the mathematical or conceptual difficulty of the problem can vary depending on the numerical values of the parameters of the problem. The application permits to easily select groups of seeds that yield to numerical variations with similar mathematical or conceptual difficulty. This represents an advantage over a randomised task assignment where students are asked to solve tasks with different difficulty.

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Starting on June 2011, NGCPV is the first project funded jointly between the European Commission (EC) and the New Energy and Industrial Technology Development Organization (NEDO) of Japan to research on new generation concentration photovoltaics (CPV). The Project, through a collaborative research between seven European and nine Japanese leading research centers in the field of CPV, aims at lowering the cost of the CPVproduced photovoltaic kWh down to 5 ?cents. The main objective of the project is to improve the present concentrator cell, module and system efficiency, as well as developing advanced characterization tools for CPV components and systems. As particular targets, the project aims at achieving a cell efficiency of at least 45% and a CPV module with an efficiency greater than 35%. This paper describes the R&D activities that are being carried out within the NGCPV project and summarizes some of the most relevant results that have already been attained, for instance: the manufacturing of a 44.4% world record efficiency triple junction solar cell (by Sharp Corp.) and the installation of a 50 kWp experimental CPV plant in Spain, which will be used to obtain accurate forecasts of the energy produced at system level.

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Collaborative hardening and hardware redundancy are nowadays the most interesting solutions in terms of fault tolerance achieved and low extra cost imposed to the project budget. Thanks to the powerful and cheap digital devices that are available in the market, extra processing capabilities can be used for redundant tasks, not only in early data processing (sensed data) but also in routing and interfacing1