937 resultados para chip
Resumo:
We propose a simple single-layer magnetic microtrap configuration which can trap an array of magnetically-trapped Bose-Einstein condensate. The configuration consists of two series of parallel wires perpendicular to each other and all of the crossing points are cut off for maintaining the uniformity of the current. We analyse the trapping potential, the position of trapping centres and the uniformity of the array of the traps. The trapping depth and trapping frequency with different parameters are also calculated. Lastly, the effect of the cut-off crossing points, dissipate power, chip production are introduced concisely.
Resumo:
We demonstrate the guiding of neutral atoms with two parallel microfabricated current-carrying wires on the atom chip and a vertical magnetic bias field. The atoms are guided along a magnetic field minimum parallel to the current-carrying wires and confined in the other two directions. We describe in detail how the precooled atoms are efficiently loaded into the two-wire guide. We present a detailed experimental study of the motional properties of the atoms in the guide and the relationship between the location of the guide and the vertical bias field. This two-wire guide with vertical bias field can be used to realize large area atom interferometer.
Resumo:
We investigate a planar ion chip design with a two-dimensional array of linear ion traps for the scalable quantum information processor. The segmented electrodes reside in a single plane on a substrate and a grounded metal plate, a combination of appropriate rf and DC potentials are applied to them for stable ion confinement, and the trap axes are located above the surface at a distance controlled by the electrodes' lateral extent and the substrate's height as discussed. The potential distributions are calculated using static electric field qualitatively. This architecture is conceptually simple and many current microfabrication techniques are feasible for the basic structure. It may provide a promising route for scalable quantum computers.
Resumo:
[EN] This paper reports an innovative technique for reagents storage in microfluidic devices by means of a one-step UV-photoprintable ionogel-based microarray on non-modified polymeric substrates. Although the ionogel and the ink-jet printing technology are well published, this is the first study where both are used for long-term reagent storage in lab-on-a-chip devices. This technology for reagent storage is perfectly compatible with mass production fabrication processes since pre-treatment of the device substrate is not necessary and inkjet printing allows for an efficient reagent deposition process. The functionality of this microarray is demonstrated by testing the release of biotin-647 after being stored for 1 month at room temperature. Analysis of the fluorescence of the ionogel-based microarray that contains biotin-647 demonstrated that 90% of the biotin-647 present was released from the ionogel-based microarray after pumping PBS 0.1% Tween at 37 °C. Moreover, the activity of biotin-647 after being released from the ionogel-based microarray was investigated trough the binding capability of this biotin to a microcontact printed chip surface with avidin. These findings pave the way for a novel, one-step, cheap and mass production on-chip reagents storage method applicable to other reagents such as antibodies and proteins and enzymes.
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228 p.
Resumo:
The direct deposition of carbon nanotubes on CMOS microhotplates is demonstrated in this paper. Tungsten microhotplates, fabricated on thin SOI membranes aside CMOS control circuitry, are used to locally grow carbon nanotubes by chemical vapour deposition. Unlike bulk heating of the entire chip, which could cause degradation to CMOS devices and interconnects due to high growth temperatures in excess of 500 °C, this novel technique allows carbon nanotubes to be grown on-chip in localized regions. The microfabricated heaters are thermally isolated from the rest of the CMOS chip as they are on the membranes. This allows carbon nanotubes to be grown alongside CMOS circuitry on the same wafer without any external heating, thus enabling new applications (e.g. smart gas sensing) where the integration of CMOS and carbon nanotubes is required.