962 resultados para Vitesse de conduction
Resumo:
We characterized the electrical conductance of well-structured multi-walled carbon nanotubes (MWCNTs) which had post-treated by a rapid vacuum arc thermal annealing process and structure defects in these nanotubes are removed. We found that the after rapid vacuum arc annealing, the conductivity of well-structured MWCNTs can be improved by an order of magnitude. We also investigated the conductivity of MWCNTs bundle by the variation of temperatures. These results show that the conductance of annealed defect-free MWCNTs is sensitive to temperature imply the phonon scatting dominated the electron conductions. Compare to the well-structured MWCNTs, the defect scattering dominated the electron conduction in the as-grown control sample which has large amount of structure defects. A detail measurement of electron conduction from an individual well-structured MWCNT shows that the conductivity increases with temperatures which imply such MWCNTs exhibited semiconductor properties. We also produced back-gated field-effect transistors using these MWCNTs. It shows that the well-structured MWCNT can act as p-type semiconductor. © 2010 IEEE.
Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature
Resumo:
Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of ~10nm Si nanocrystals, separated by SiO 2 regions. At 300 K, strong Coulomb staircases are seen in the drain-source current-voltage (I ds-V ds) characteristics, and single-electron oscillations are seen in the drain-source current-gate voltage (I ds-V ds) characteristics. From 300-20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using singleelectron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction " bottleneck", suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, ~20k BT at 300 K. © 2012 The Japan Society of Applied Physics.
Conduction Bottleneck in Silicon Nanochain Single Electron Transistors Operating at Room Temperature
Resumo:
Surface temperature measurements from two discs of a gas turbine compressor rig are used as boundary conditions for the transient conduction solution (inverse heat transfer analysis). The disc geometry is complex, and so the finite element method is used. There are often large radial temperature gradients on the discs, and the equations are therefore solved taking into account the dependence of thermal conductivity on temperature. The solution technique also makes use of a multigrid algorithm to reduce the solution time. This is particularly important since a large amount of data must be analyzed to obtain correlations of the heat transfer. The finite element grid is also used for a network analysis to calculate the radiant heat transfer in the cavity formed between the two compressor discs. The work discussed here proved particularly challenging as the disc temperatures were only measured at four different radial locations. Four methods of surface temperature interpolation are examined, together with their effect on the local heat fluxes. It is found that the choice of interpolation method depends on the available number of data points. Bessel interpolation gives the best results for four data points, whereas cubic splines are preferred when there are considerably more data points. The results from the analysis of the compressor rig data show that the heat transfer near the disc inner radius appears to be influenced by the central throughflow. However, for larger radii, the heat transfer from the discs and peripheral shroud is found to be consistent with that of a buoyancy-induced flow.
Resumo:
We investigate the electrical properties of silicon-on-insulator (SOI) photonic crystals as a function of both doping level and air filling factor. The resistance trends can be clearly explained by the presence of a depletion region around the sidewalls of the holes that is caused by band pinning at the surface. To understand the trade-off between the carrier transport and the optical losses due to free electrons in the doped SOI, we also measured the resonant modes of L3 photonic crystal nanocavities and found that surprisingly high doping levels, up to 1018 / cm3, are acceptable for practical devices with Q factors as high as 4× 104. © 2011 American Institute of Physics.
Resumo:
The fabrication and functionality of a 21 cm graphene-based transverse electron emission display panel is presented. A screen-printed triode edge electron emission geometry has been developed based on chemical vapor deposited (CVD) graphene supported on vertically aligned carbon nanotubes (CNT) necessary to minimize electrostatic shielding induced by the proximal bulk substrate. Integrated ZnO tetrapod electron scatterers have been shown to increase the emission efficiency by more than 90%. Simulated electron trajectories validate the observed emission characteristics with driving voltages less than 60 V. Fabricated display panels have shown real-time video capabilities that are hysteresis free (<0.2%), have extremely stable lifetimes (<3% variation over 10 h continuous operation) in addition to rapid temporal responses (<1 ms). © 2013 Elsevier Ltd. All rights reserved.