Editorial optical computing circuits, devices and systems

Information forms the basis of modern technology. To meet the ever-increasing demand for information, means have to be devised for a more efficient and better-equipped technology to intelligibly process data. Advances in photonics have made their impact on each of the four key applications in information processing, i.e., acquisition, transmission, storage and processing of information. The inherent advantages of ultrahigh bandwidth, high speed and low-loss transmission has already established fiber-optics as the backbone of communication technology. However, the optics to electronics inter-conversion at the transmitter and receiver ends severely limits both the speed and bit rate of lightwave communication systems. As the trend towards still faster and higher capacity systems continues, it has become increasingly necessary to perform more and more signal-processing operations in the optical domain itself, i.e., with all-optical components and devices that possess a high bandwidth and can perform parallel processing functions to eliminate the electronic bottleneck.

New static 3-step distance relay

A new static 3-step distance relay based on the principle of multi-input phase comparison is described in the paper. Design principles and typical discriminating and logic circuits are described for the new relaying system. The relaying system uses semiconductor circuits throughout and features high speed and good performance. The comparator model, which effects multi-input phase comparison, has been devised to provide reliable pickup for closein faults, and to achieve an improved polar characteristic in the complex- impedance plane, which fits around only the fault area of a transmission line. Operating time of the relay is less than 1 cycle for unbalanced faults, and less than a halfcycle for 3-phase faults. Protective circuits have also been added to detect power swing and to block tripping for a predetermined number of power-swing cycles. The operating characteristics of the relay, as expressed by accuracy/range charts, are presented.

Modified McMurray Inverter with Pulse Forming Network Commutation Circuits

The modified McMurray Inverter with Pulse Forming Network (PFN) has been explained. The current and voltage waveshapes of the PFN commutation ci rcuit have been compared with conventional L-commutation circuit. The design method of PFN has been explained. Advantages of this type of commutation have been discussed. Experimental results are given.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Self Repair in Circuits-Automating Open Fault Repair in Integrated Circuits Using Field-Induced Aggregation of Carbon Nanotubes

This paper presents studies on the use of carbon nanotubes dispersed in an insulating fluid to serve as an automaton for healing open-circuit interconnect faults in integrated circuits. The physics behind the repair mechanism is the electric-field-induced diffusion limited aggregation. On the occurrence of an open fault, the repair is automatically triggered due to the presence of an electric field across the gap. We perform studies on the repair time as a function of the electric field and dispersion concentrations with the above application in mind.

Comparison of 3-phase, 3-level UPF rectifier circuits for high power applications

This paper presents an analysis and comparison between two circuit topologies of the 3-phase, 3-level unity power factor (Vienna) rectifier on the basis of packaging issues and semiconductor power losses. The analysis indicates the suitability of one particular circuit variant due to restrictions on switching frequency at higher power levels. A comparison is also done between hysteresis and carrier based PWM strategies for current control of the rectifier, along with experimental evaluation of the control strategies on a hardware prototype of the rectifier. The comparison indicates that the carrier based modulation strategy is better suited for use with higher order filters that are utilized in high power applications.

Operand Isolation Circuits with Reduced Overhead for Low Power Data-Path Design

Dynamic power dissipation due to redundant switching is an important metric in data-path design. This paper focuses on the use of ingenious operand isolation circuits for low power design. Operand isolation attempts to reduce switching by clamping or latching the output of a first level of combinational circuit. This paper presents a novel method using power supply switching wherein both PMOS and NMOS stacks of a circuit are connected to the same power supply. Thus, the output gets clamped or latched to the power supply value with minimal leakage. The proposed circuits make use of only two transistors to clamp the entire Multiple Input Multiple Output (MIMO) block. Also, the latch-based designs have higher drive strength in comparison to the existing methods. Simulation results have shown considerable area reduction in comparison to the existing techniques without increasing timing overhead.

Gamma oscillations in the midbrain spatial attention network: linking circuits to function

Gamma-band (25-140 Hz) oscillations are ubiquitous in mammalian forebrain structures involved in sensory processing, attention, learning and memory. The optic tectum (01) is the central structure in a midbrain network that participates critically in controlling spatial attention. In this review, we summarize recent advances in characterizing a neural circuit in this midbrain network that generates large amplitude, space-specific, gamma oscillations in the avian OT, both in vivo and in vitro. We describe key physiological and pharmacological mechanisms that produce and regulate the structure of these oscillations. The extensive similarities between midbrain gamma oscillations in birds and those in the neocortex and hippocampus of mammals, offer important insights into the functional significance of a midbrain gamma oscillatory code.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.