Reengenharia do framework cosmos: uma solução para prover suporte e adaptações abertas.

Self-adaptive software system is able to change its structure and/or behavior at runtime due to changes in their requirements, environment or components. One way to archieve self-adaptation is the use a sequence of actions (known as adaptation plans) which are typically defined at design time. This is the approach adopted by Cosmos - a Framework to support the configuration and management of resources in distributed environments. In order to deal with the variability inherent of self-adaptive systems, such as, the appearance of new components that allow the establishment of configurations that were not envisioned at development time, this dissertation aims to give Cosmos the capability of generating adaptation plans of runtime. In this way, it was necessary to perform a reengineering of the Cosmos Framework in order to allow its integration with a mechanism for the dynamic generation of adaptation plans. In this context, our work has been focused on conducting a reengineering of Cosmos. Among the changes made to in the Cosmos, we can highlight: changes in the metamodel used to represent components and applications, which has been redefined based on an architectural description language. These changes were propagated to the implementation of a new Cosmos prototype, which was then used for developing a case study application for purpose of proof of concept. Another effort undertaken was to make Cosmos more attractive by integrating it with another platform, in the case of this dissertation, the OSGi platform, which is well-known and accepted by the industry

Geração de processos WS-BPEL com base em um algoritmo de reescrita de regras

Web services are computational solutions designed according to the principles of Service Oriented Computing. Web services can be built upon pre-existing services available on the Internet by using composition languages. We propose a method to generate WS-BPEL processes from abstract specifications provided with high-level control-flow information. The proposed method allows the composition designer to concentrate on high-level specifi- cations, in order to increase productivity and generate specifications that are independent of specific web services. We consider service orchestrations, that is compositions where a central process coordinates all the operations of the application. The process of generating compositions is based on a rule rewriting algorithm, which has been extended to support basic control-flow information.We created a prototype of the extended refinement method and performed experiments over simple case studies

Geração de interfaces de usuário de sistemas Web para múltiplos dispositivos com o uso de componentes de IU

This work presents an User Interface (UI) prototypes generation process to the softwares that has a Web browser as a plataform. This process uses UI components more complex than HTML elements. To described this components more complex this work suggest to use the XICL (eXtensinble User Interface Components Language). XICL is a language, based on XML syntax, to describe UI Components and IUs. XICL promotes extensibility and reusability in the User Interface development process. We have developed two compiler. The first one compiles IMML (Interactive Message Modeling Language) code and generates XICL code. The second one compiles XICL code and generates DHTML code

The first electronic polytomous key to the world species of the subgenus Typhlodromus (Anthoseius) de Leon (Acari: Phytoseiidae)

This paper describes the first polytomous computerised identification key within the family Phytoseiidae. It applies to the females of the world species of the subgenus Typhlodromus (Anthoseius) de Leon. This group is one of the largest within the family Phytoseiidae and the sub-family Typhlodrominae, with nearly 350 species currently recognised worldwide. No identification tool of these species exists at the world level, which makes their identification very difficult and unsecure. Thirty five characters were used to characterise each of the 343 species. Among these characters, 14 are discrete and 21 are continuous. The polytomous key was constructed using the free software DELTA 1.04 (DEscription Language for TAxonomy) and is freely available at the web site: http://www1.montpellier.inra.fr/CBGP/phytoseiidae/anthoseiuskeypresentation.html. We hope that this work will open new perspectives for the identification of species of other genera (especially the largest ones, e.g. Neoseiulus, Euseius, Amblyseius) which contains more than 150 species and for which no key presently exists. We also expect that the present work will make the identification of the world species of Typhlodromus (Anthoseius) easier and more secure. Finally, we expect a contribution from the whole Phytoseiidae scientist community to improve subsequent versions of the key.

Arquitetura multiprocessada e reconfigurável para a síntese de redes de Petri em hardware

Uma arquitetura reconfigurável e multiprocessada para a implementação física de Redes de Petri foi desenvolvida em VHDL e mapeada sobre um FPGA. Convencionalmente, as Redes de Petri são transformadas em uma linguagem de descrição de hardware no nível de transferências entre registradores e um processo de síntese de alto nível é utilizado para gerar as funções booleanas e tabelas de transição de estado para que se possa, finalmente, mapeá-las num FPGA (Morris et al., 2000) (Soto and Pereira, 2001). A arquitetura proposta possui blocos lógicos reconfiguráveis desenvolvidos exclusivamente para a implementação dos lugares e das transições da rede, não sendo necessária a descrição da rede em níveis de abstração intermediários e nem a utilização de um processo de síntese para realizar o mapeamento da rede na arquitetura. A arquitetura permite o mapeamento de modelos de Redes de Petri com diferenciação entre as marcas e associação de tempo no disparo das transições, sendo composta por um arranjo de processadores reconfiguráveis, cada um dos quais representando o comportamento de uma transição da Rede de Petri a ser mapeada e por um sistema de comunicação, implementado por um conjunto de roteadores que são capazes de enviar pacotes de dados de um processador reconfigurável a outro. A arquitetura proposta foi validada num FPGA de 10.570 elementos lógicos com uma topologia que permitiu a implementação de Redes de Petri de até 9 transições e 36 lugares, atingindo uma latência de 15,4ns e uma vazão de até 17,12GB/s com uma freqüência de operação de 64,58MHz.

A multi-cell variable frequency interleaved ZCS boost rectifier digitally controlled by FPGA

This paper presents a multi-cell single-phase high power factor boost rectifier in interleave connection, operating in critical conduction mode, employing a soft-switching technique, and controlled by Field Programmable Gate Array (FPGA). The soft-switching technique is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-vohage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the interleaving technique, the rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for all interleaved cells, and a closed-loop to provide the output voltage regulation, like as a preregulator rectifier. Experimental results are presented for a implemented prototype with two and with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.

A phase-shifting control for variable frequency multi-cells interleaved boost pre-regulator based on FPGA device

In this paper were investigated phase-shift control strategies applied to a four cells interleaved high input-power-factor pre-regulator boost rectifier, operating in critical conduction mode, using a non-dissipative commutation cells and frequency modulation. The digital control has been developed using a hardware description language (VHDL) and implemented using the XC2S200E-SpartanII-E/Xilinx FPGA, performing a true critical conduction operation mode for a generic number of interleaved cells. Experimental results are presented, in order to verify the feasibility and performance of the proposed digital control, through the use of a Xilinx FPGA device.

An AC voltage regulator with high-power-factor, and control using a FPGA device

This paper presents the analysis, design, simulation, and experimental results for a high frequency high Power-Factor (PF) AC (Alternate Current) voltage regulator, using a Sepic converter as power stage. The control technique employed to impose a sinusoidal input current waveform, with low Total Harmonic Distortion (THD), is the sinusoidal variable hysteresis control. The control technique was implemented in a FPGA (Field Programmable Gate Array) device, using a Hardware Description Language (VHDL). Through the use of the proposed control technique, the AC voltage regulator performs active power-factor correction, and low THD in the input current, for linear and non-linear loads, satisfying the requirements of the EEC61000-3-2 standards. Experimental results from an example prototype, designed for 300W of nominal output power, 50kHz (switching frequency), and 127Vrms of nominal input and output voltages, are presented in order to validate the proposed AC regulator. © 2005 IEEE.

Implementation of filters for image pre-processing for leaf analyses in plantations

In this work an image pre-processing module has been developed to extract quantitative information from plantation images with various degrees of infestation. Four filters comprise this module: the first one acts on smoothness of the image, the second one removes image background enhancing plants leaves, the third filter removes isolated dots not removed by the previous filter, and the fourth one is used to highlight leaves' edges. At first the filters were tested with MATLAB, for a quick visual feedback of the filters' behavior. Then the filters were implemented in the C programming language. At last, the module as been coded in VHDL for the implementation on a Stratix II family FPGA. Tests were run and the results are shown in this paper. © 2008 Springer-Verlag Berlin Heidelberg.

A true programmable HPF hybrid three-phase rectifier

In this paper is proposed and analyzed a digital hysteresis modulation using a FPGA (Field Programmable Gate Array) device and VHDL (Hardware Description Language), applied at a hybrid three-phase rectifier with almost unitary input power factor, composed by parallel SEPIC controlled single-phase rectifiers connected to each leg of a standard 6-pulses uncontrolled diode rectifier. The digital control allows a programmable THD (Total Harmonic Distortion) at the input currents, and it makes possible that the power rating of the switching-mode converters, connected in parallel, can be a small fraction of the total average output power, in order to obtain a compact converter, reduced input current THD and almost unitary input power factor. The proposed digital control, using a FPGA device and VHDL, offers an important flexibility for the associated control technique, in order to obtain a programmable PFC (Power Factor Correction) hybrid three-phase rectifier, in agreement with the international standards (IEC, and IEEE), which impose limits for the THD of the AC (Alternate Current) line input currents. Finally, the proposed control strategy is verified through experimental results from an implemented prototype. ©2008 IEEE.

HPF boost interleaved operating in discontinuous conduction mode for trolleybus application

This paper deals with results of a research and development (R&D) project in cooperation with Electric Power Distribution Company in São Paulo (Brazil) regarding the development and experimental analysis of a new concept of power drive system suitable for application in traction systems of electrical vehicles pulled by electrical motors, which can be powered by urban DC or AC distribution networks. The proposed front-end structure is composed by five boost power cells in interleaving connection, operating in discontinuous conduction mode as AC-DC converter, or as DC-DC converter, in order to provide the proper DC output voltage range required by DC or AC adjustable speed drivers. Therefore, when supplied by single-phase AC distribution networks, and operating as AC-DC converter, it is capable to provide high power factor, reduced harmonic distortion in the input current, complying with the restrictions imposed by the IEC 61000-3-4 standards resulting in significant improvements for the trolleybuses systems efficiency and for the urban distribution network costs. Considering the compliance with input current restrictions imposed by IEC 61000-3-4 standards, two digital control strategies were evaluated. The digital controller has been implemented using a low cost FPGA (XC3S200) and developed totally using a hardware description language VHDL and fixed point arithmetic. Experimental results from a 15 kW low power scale prototype operating in DC and AC conditions are presented, in order to verify the feasibility and performance of the proposed system. © 2009 IEEE.

Ambiente computacional para projetos de sistemas com tecnologia mista

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Algoritmos de detecção de bordas implementados em FPGA

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Aplicando lógica fuzzy no controle de robôs móveis usando dispositivos lógicos programáveis e a linguagem VHDL

Pós-graduação em Engenharia Elétrica - FEIS

Um sistema eletrônico de 2kW para emulação/simulação experimental da característica estática de saída, tensão (versus) corrente, de sistemas de geração com células combustível tipo PEM

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)