Plant architecture

Plant architecture is species specific, indicating that it is under strict genetic control. Although it is also influenced by environmental conditions such as light, temperature, humidity and nutrient status, here we wish to focus only on the endogenous regulatory principles that control plant architecture. We summarise recent progress in the understanding of the basic patterning mechanisms involved in the regulation of leaf arrangement, the genetic regulation of meristem determinacy, i.e. the decision to stop or continue growth, and the control of branching during vegetative and generative development. Finally, we discuss the basis of leaf architecture and the role of cell division and cell growth in morphogenesis.

Reconstructing the subsurface ocean decadal variability using surface nudging in a perfect model framework

Initialising the ocean internal variability for decadal predictability studies is a new area of research and a variety of ad hoc methods are currently proposed. In this study, we explore how nudging with sea surface temperature (SST) and salinity (SSS) can reconstruct the threedimensional variability of the ocean in a perfect model framework. This approach builds on the hypothesis that oceanic processes themselves will transport the surface information into the ocean interior as seen in ocean-only simulations. Five nudged simulations are designed to reconstruct a 150 years ‘‘target’’ simulation, defined as a portion of a long control simulation. The nudged simulations differ by the variables restored to, SST or SST + SSS, and by the area where the nudging is applied. The strength of the heat flux feedback is diagnosed from observations and the restoring coefficients for SSS use the same time-scale. We observed that this choice prevents spurious convection at high latitudes and near sea-ice border when nudging both SST and SSS. In the tropics, nudging the SST is enough to reconstruct the tropical atmosphere circulation and the associated dynamical and thermodynamical impacts on the underlying ocean. In the tropical Pacific Ocean, the profiles for temperature show a significant correlation from the surface down to 2,000 m, due to dynamical adjustment of the isopycnals. At mid-tohigh latitudes, SSS nudging is required to reconstruct both the temperature and the salinity below the seasonal thermocline. This is particularly true in the North Atlantic where adding SSS nudging enables to reconstruct the deep convection regions of the target. By initiating a previously documented 20-year cycle of the model, the SST + SSS nudging is also able to reproduce most of the AMOC variations, a key source of decadal predictability. Reconstruction at depth does not significantly improve with amount of time spent nudging and the efficiency of the surface nudging rather depends on the period/events considered. The joint SST + SSS nudging applied verywhere is the most efficient approach. It ensures that the right water masses are formed at the right surface density, the subsequent circulation, subduction and deep convection further transporting them at depth. The results of this study underline the potential key role of SSS for decadal predictability and further make the case for sustained largescale observations of this field.

Regulation of phyllotaxis

Plant architecture is characterized by a high degree of regularity. Leaves, flowers and floral organs are arranged in regular patterns, a phenomenon referred to as phyllotaxis. Regular phyllotaxis is found in virtually all higher plants, from mosses, over ferns, to gymnosperms and angiosperms. Due to its remarkable precision, its beauty and its accessibility, phyllotaxis has for centuries been the object of admiration and scientific examination. There have been numerous hypotheses to explain the nature of the mechanistic principle behind phyllotaxis, however, not all of them have been amenable to experimental examination. This is due mainly to the delicacy and small size of the shoot apical meristem, where plant organs are formed and the phyllotactic patterns are laid down. Recently, the combination of genetics, molecular tools and micromanipulation has resulted in the identification of auxin as a central player in organ formation and positioning. This paper discusses some aspects of phyllotactic patterns found in nature and summarizes our current understanding of the regulatory mechanism behind phyllotaxis.

Emissions Control and the Regulation of Product Markets: The Case of Automobiles

The paper investigates alternative policies to regulate emissions from polluting product markets, specifically considering the case of the automobiles market. The two policies we consider are: a quota that limits the quantity produced of the polluting model and a more flexible average efficiency standard that requires a minimum energy efficiency across all models produced by a firm, similar to the US Corporate Average Fuel Economy (CAFE) standards. We use a duopoly model of vertical differentiation where firms produce both an economy (i.e., low polluting) version and a luxury (i.e., high polluting) version of a given product. We show that while a quota can raise firm profit over a certain range, CAFE always reduces firm profit relative to the pre-regulation. We also show that while the quota reduces emissions, it is possible that emissions increase under CAFE. The optimal policy choice will depend on the magnitude of unit damages. We show that when unit damages are sufficiently high, the quota policy is more efficient than the average efficiency standard. This suggests that instead of tightening CAFE to limit damages from emissions, policy makers can shift to a quota policy which is both welfare enhancing and more profitable for firms.

A Description Framework and Event-Driven Architecture for the Semantic Web and Semantic Grid

In this introductory chapter we put in context and give a brief outline of the work that we thoroughly present in the rest of the dissertation. We consider this work divided in two main parts. The first part is the Firenze Framework, a knowledge level description framework rich enough to express the semantics required for describing both semantic Web services and semantic Grid services. We start by defining what the Semantic Grid is and its relation with the Semantic Web; and the possibility of their convergence since both initiatives have become mainly service-oriented. We also introduce the main motivators of the creation of this framework, one is to provide a valid description framework that works at knowledge level; the other to provide a description framework that takes into account the characteristics of Grid services in order to be able to describe them properly. The other part of the dissertation is devoted to Vega, an event-driven architecture that, by means of proposed knowledge level description framework, is able to achieve high scale provisioning of knowledge-intensive services. In this introductory chapter we portrait the anatomy of a generic event-driven architecture, and we briefly enumerate their main characteristics, which are the reason that make them our choice.

Máquinas o atmósferas: La estética de la energía en la arquitectura, 1750-2000 = From Machines to Atmospheres: The Aesthetics of Energy in Architecture, 1750-2000

La energía es ya un tema arquitectónico, pero su incorporación al proyecto ha sido hasta ahora fundamentalmente técnica, dando pie a una especie de funcionalismo ecológico cuyo destino es acaso repetir los errores de los viejos funcionalismos en su confianza de encontrar modos ‘objetivos’ de transmutar la energía en forma construida, pero sin que en tal proceso parezca haber hueco para mediaciones de tipo estético. Sin embargo, son precisamente tales mediaciones las que necesitan analizarse para que la adopción de los temas energéticos resulte fructífera en la arquitectura, y asimismo para dar cuenta de otras perspectivas complementarias —filosóficas, científicas, artísticas— que hoy forman el complejo campo semántico de la energía. Partiendo de la fecha de 1750 —que da comienzo simbólicamente al proceso de contaminaciones ‘modernas’ entre la arquitectura y otras disciplinas—, esta tesis analiza los diferentes modos con los que proyectos y edificios han expresado literal y analógicamente ciertos temas o ideales energéticos, demostrando la existencia de una ‘estética de la energía’ en la arquitectura y también de una tradición proyectual e intelectual sostenida en ella. Con este fin, se han seleccionados siete metáforas que vinculan tanto técnica como ideológicamente a la arquitectura con la energía: la metáfora de la máquina, asociada al ideal de movimiento y la autorregulación; las metáforas del arabesco, del cristal y del organismo, afines entre sí en su modo de dar cuenta del principio de la morfogénesis o energía creadora de la naturaleza; la metáfora de la actividad interna de los materiales; la metáfora del gradiente, que expresa la condición térmica y climática de la arquitectura, y, finalmente, la de la atmósfera que, recogiendo los sentidos anteriores, los actualiza en el contexto de la estética contemporánea. La selección de estas siete metáforas se ha llevado a cabo después de un barrido exhaustivo de la bibliografía precedente, y ha estructurado un relato cuyo método combina la perspectiva general —que permite cartografiar las continuidades históricas— con la cercana —que atiende a las problemas específicos de cada tema o metáfora—, complementándolas con una aproximación de sesgo iconográfico cuyo propósito es incidir en los vínculos que se dan entre lo ideológico y lo morfológico. El análisis ha puesto de manifiesto cómo detrás de cada una de estas metáforas se oculta un principio ideológico común —la justificación de la arquitectura desde planteamientos externos procedentes de la ciencia, la filosofía y el arte—, y cómo en cada uno de los casos estudiados las asimilaciones más fructíferas de la energía se han producido según mecanismos de mímesis analógica que inciden más en los procesos que en las formas que estos generan, y que en último término son de índole estética, lo cual constituye un indicio de los métodos de la arquitectura por venir. ABSTRACT Although it is already an architectural theme, the matter of incorporating energy into projects has up to now been mainly technical, giving rise to a kind of ecological functionalism which may be bound to old funcionalist mistakes in hopes of finding “objective” ways of transmuting energy into built forms without aesthetic considerations. However, it is precisely such considerations that need to be analyzed if the adoption of energy issues in architecture is to bear fruit and also to account for other complementary perspectives – philosophical, scientific, artistic – which today form the complex fabric of the energy semantic field. Beginning in 1750 – symbolic start of ‘modern’ contaminations between architecture and other disciplines –, this thesis analyzes the different ways in which projects and buildings have literally and analogically expressed certain subjects or ideals on energy, and demonstrates the existence of an “aesthetics of energy” in architecture, as well as of an intellectual and design tradition based on such aesthetics. For this purpose, seven metaphors are selected to link energy to architecture both technically and ideologically: the machine’s metaphor, associated with the ideal of mouvement and self-regulation; the arabesque, glass and the organism’s metaphors, which account for the morphogenesis principle, i.e. creative energy of nature; the metaphor linked to matter and the ideal of internal activity; the gradient’s metaphor, which expressed the thermal and climatic condition of architecture, and, finally, that of the atmosphere which, collecting the above meanings, updates them in the context of contemporary aesthetics. The selection of these seven metaphors was carried out after a thorough scan of the preceding literature, and has structured a reasoning that combines the overview method – which accounts for historical continuities – with the nearby one – which meets the specifics problems of each theme or metaphor –, both supplemented with an iconographic bias, the purpose of which is to visually express the links existing between the ideological and the morphological. So presented, the analysis shows how, behind each of these metaphors, lies a common ideological principle – the justification of architecture from scientific, philosophical and artistic “external” angles –, and how in each of the studied cases the most successful assimilation of energy were those produced by aesthetic mechanisms of analogical mimesis not focused in forms but in processes that generate them: an indication of the methods of architecture to come.

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

Esta tesis doctoral se enmarca dentro del campo de los sistemas embebidos reconfigurables, redes de sensores inalámbricas para aplicaciones de altas prestaciones, y computación distribuida. El documento se centra en el estudio de alternativas de procesamiento para sistemas embebidos autónomos distribuidos de altas prestaciones (por sus siglas en inglés, High-Performance Autonomous Distributed Systems (HPADS)), así como su evolución hacia el procesamiento de alta resolución. El estudio se ha llevado a cabo tanto a nivel de plataforma como a nivel de las arquitecturas de procesamiento dentro de la plataforma con el objetivo de optimizar aspectos tan relevantes como la eficiencia energética, la capacidad de cómputo y la tolerancia a fallos del sistema. Los HPADS son sistemas realimentados, normalmente formados por elementos distribuidos conectados o no en red, con cierta capacidad de adaptación, y con inteligencia suficiente para llevar a cabo labores de prognosis y/o autoevaluación. Esta clase de sistemas suele formar parte de sistemas más complejos llamados sistemas ciber-físicos (por sus siglas en inglés, Cyber-Physical Systems (CPSs)). Los CPSs cubren un espectro enorme de aplicaciones, yendo desde aplicaciones médicas, fabricación, o aplicaciones aeroespaciales, entre otras muchas. Para el diseño de este tipo de sistemas, aspectos tales como la confiabilidad, la definición de modelos de computación, o el uso de metodologías y/o herramientas que faciliten el incremento de la escalabilidad y de la gestión de la complejidad, son fundamentales. La primera parte de esta tesis doctoral se centra en el estudio de aquellas plataformas existentes en el estado del arte que por sus características pueden ser aplicables en el campo de los CPSs, así como en la propuesta de un nuevo diseño de plataforma de altas prestaciones que se ajuste mejor a los nuevos y más exigentes requisitos de las nuevas aplicaciones. Esta primera parte incluye descripción, implementación y validación de la plataforma propuesta, así como conclusiones sobre su usabilidad y sus limitaciones. Los principales objetivos para el diseño de la plataforma propuesta se enumeran a continuación: • Estudiar la viabilidad del uso de una FPGA basada en RAM como principal procesador de la plataforma en cuanto a consumo energético y capacidad de cómputo. • Propuesta de técnicas de gestión del consumo de energía en cada etapa del perfil de trabajo de la plataforma. •Propuestas para la inclusión de reconfiguración dinámica y parcial de la FPGA (por sus siglas en inglés, Dynamic Partial Reconfiguration (DPR)) de forma que sea posible cambiar ciertas partes del sistema en tiempo de ejecución y sin necesidad de interrumpir al resto de las partes. Evaluar su aplicabilidad en el caso de HPADS. Las nuevas aplicaciones y nuevos escenarios a los que se enfrentan los CPSs, imponen nuevos requisitos en cuanto al ancho de banda necesario para el procesamiento de los datos, así como en la adquisición y comunicación de los mismos, además de un claro incremento en la complejidad de los algoritmos empleados. Para poder cumplir con estos nuevos requisitos, las plataformas están migrando desde sistemas tradicionales uni-procesador de 8 bits, a sistemas híbridos hardware-software que incluyen varios procesadores, o varios procesadores y lógica programable. Entre estas nuevas arquitecturas, las FPGAs y los sistemas en chip (por sus siglas en inglés, System on Chip (SoC)) que incluyen procesadores embebidos y lógica programable, proporcionan soluciones con muy buenos resultados en cuanto a consumo energético, precio, capacidad de cómputo y flexibilidad. Estos buenos resultados son aún mejores cuando las aplicaciones tienen altos requisitos de cómputo y cuando las condiciones de trabajo son muy susceptibles de cambiar en tiempo real. La plataforma propuesta en esta tesis doctoral se ha denominado HiReCookie. La arquitectura incluye una FPGA basada en RAM como único procesador, así como un diseño compatible con la plataforma para redes de sensores inalámbricas desarrollada en el Centro de Electrónica Industrial de la Universidad Politécnica de Madrid (CEI-UPM) conocida como Cookies. Esta FPGA, modelo Spartan-6 LX150, era, en el momento de inicio de este trabajo, la mejor opción en cuanto a consumo y cantidad de recursos integrados, cuando además, permite el uso de reconfiguración dinámica y parcial. Es importante resaltar que aunque los valores de consumo son los mínimos para esta familia de componentes, la potencia instantánea consumida sigue siendo muy alta para aquellos sistemas que han de trabajar distribuidos, de forma autónoma, y en la mayoría de los casos alimentados por baterías. Por esta razón, es necesario incluir en el diseño estrategias de ahorro energético para incrementar la usabilidad y el tiempo de vida de la plataforma. La primera estrategia implementada consiste en dividir la plataforma en distintas islas de alimentación de forma que sólo aquellos elementos que sean estrictamente necesarios permanecerán alimentados, cuando el resto puede estar completamente apagado. De esta forma es posible combinar distintos modos de operación y así optimizar enormemente el consumo de energía. El hecho de apagar la FPGA para ahora energía durante los periodos de inactividad, supone la pérdida de la configuración, puesto que la memoria de configuración es una memoria volátil. Para reducir el impacto en el consumo y en el tiempo que supone la reconfiguración total de la plataforma una vez encendida, en este trabajo, se incluye una técnica para la compresión del archivo de configuración de la FPGA, de forma que se consiga una reducción del tiempo de configuración y por ende de la energía consumida. Aunque varios de los requisitos de diseño pueden satisfacerse con el diseño de la plataforma HiReCookie, es necesario seguir optimizando diversos parámetros tales como el consumo energético, la tolerancia a fallos y la capacidad de procesamiento. Esto sólo es posible explotando todas las posibilidades ofrecidas por la arquitectura de procesamiento en la FPGA. Por lo tanto, la segunda parte de esta tesis doctoral está centrada en el diseño de una arquitectura reconfigurable denominada ARTICo3 (Arquitectura Reconfigurable para el Tratamiento Inteligente de Cómputo, Confiabilidad y Consumo de energía) para la mejora de estos parámetros por medio de un uso dinámico de recursos. ARTICo3 es una arquitectura de procesamiento para FPGAs basadas en RAM, con comunicación tipo bus, preparada para dar soporte para la gestión dinámica de los recursos internos de la FPGA en tiempo de ejecución gracias a la inclusión de reconfiguración dinámica y parcial. Gracias a esta capacidad de reconfiguración parcial, es posible adaptar los niveles de capacidad de procesamiento, energía consumida o tolerancia a fallos para responder a las demandas de la aplicación, entorno, o métricas internas del dispositivo mediante la adaptación del número de recursos asignados para cada tarea. Durante esta segunda parte de la tesis se detallan el diseño de la arquitectura, su implementación en la plataforma HiReCookie, así como en otra familia de FPGAs, y su validación por medio de diferentes pruebas y demostraciones. Los principales objetivos que se plantean la arquitectura son los siguientes: • Proponer una metodología basada en un enfoque multi-hilo, como las propuestas por CUDA (por sus siglas en inglés, Compute Unified Device Architecture) u Open CL, en la cual distintos kernels, o unidades de ejecución, se ejecuten en un numero variable de aceleradores hardware sin necesidad de cambios en el código de aplicación. • Proponer un diseño y proporcionar una arquitectura en la que las condiciones de trabajo cambien de forma dinámica dependiendo bien de parámetros externos o bien de parámetros que indiquen el estado de la plataforma. Estos cambios en el punto de trabajo de la arquitectura serán posibles gracias a la reconfiguración dinámica y parcial de aceleradores hardware en tiempo real. • Explotar las posibilidades de procesamiento concurrente, incluso en una arquitectura basada en bus, por medio de la optimización de las transacciones en ráfaga de datos hacia los aceleradores. •Aprovechar las ventajas ofrecidas por la aceleración lograda por módulos puramente hardware para conseguir una mejor eficiencia energética. • Ser capaces de cambiar los niveles de redundancia de hardware de forma dinámica según las necesidades del sistema en tiempo real y sin cambios para el código de aplicación. • Proponer una capa de abstracción entre el código de aplicación y el uso dinámico de los recursos de la FPGA. El diseño en FPGAs permite la utilización de módulos hardware específicamente creados para una aplicación concreta. De esta forma es posible obtener rendimientos mucho mayores que en el caso de las arquitecturas de propósito general. Además, algunas FPGAs permiten la reconfiguración dinámica y parcial de ciertas partes de su lógica en tiempo de ejecución, lo cual dota al diseño de una gran flexibilidad. Los fabricantes de FPGAs ofrecen arquitecturas predefinidas con la posibilidad de añadir bloques prediseñados y poder formar sistemas en chip de una forma más o menos directa. Sin embargo, la forma en la que estos módulos hardware están organizados dentro de la arquitectura interna ya sea estática o dinámicamente, o la forma en la que la información se intercambia entre ellos, influye enormemente en la capacidad de cómputo y eficiencia energética del sistema. De la misma forma, la capacidad de cargar módulos hardware bajo demanda, permite añadir bloques redundantes que permitan aumentar el nivel de tolerancia a fallos de los sistemas. Sin embargo, la complejidad ligada al diseño de bloques hardware dedicados no debe ser subestimada. Es necesario tener en cuenta que el diseño de un bloque hardware no es sólo su propio diseño, sino también el diseño de sus interfaces, y en algunos casos de los drivers software para su manejo. Además, al añadir más bloques, el espacio de diseño se hace más complejo, y su programación más difícil. Aunque la mayoría de los fabricantes ofrecen interfaces predefinidas, IPs (por sus siglas en inglés, Intelectual Property) comerciales y plantillas para ayudar al diseño de los sistemas, para ser capaces de explotar las posibilidades reales del sistema, es necesario construir arquitecturas sobre las ya establecidas para facilitar el uso del paralelismo, la redundancia, y proporcionar un entorno que soporte la gestión dinámica de los recursos. Para proporcionar este tipo de soporte, ARTICo3 trabaja con un espacio de soluciones formado por tres ejes fundamentales: computación, consumo energético y confiabilidad. De esta forma, cada punto de trabajo se obtiene como una solución de compromiso entre estos tres parámetros. Mediante el uso de la reconfiguración dinámica y parcial y una mejora en la transmisión de los datos entre la memoria principal y los aceleradores, es posible dedicar un número variable de recursos en el tiempo para cada tarea, lo que hace que los recursos internos de la FPGA sean virtualmente ilimitados. Este variación en el tiempo del número de recursos por tarea se puede usar bien para incrementar el nivel de paralelismo, y por ende de aceleración, o bien para aumentar la redundancia, y por lo tanto el nivel de tolerancia a fallos. Al mismo tiempo, usar un numero óptimo de recursos para una tarea mejora el consumo energético ya que bien es posible disminuir la potencia instantánea consumida, o bien el tiempo de procesamiento. Con el objetivo de mantener los niveles de complejidad dentro de unos límites lógicos, es importante que los cambios realizados en el hardware sean totalmente transparentes para el código de aplicación. A este respecto, se incluyen distintos niveles de transparencia: • Transparencia a la escalabilidad: los recursos usados por una misma tarea pueden ser modificados sin que el código de aplicación sufra ningún cambio. • Transparencia al rendimiento: el sistema aumentara su rendimiento cuando la carga de trabajo aumente, sin cambios en el código de aplicación. • Transparencia a la replicación: es posible usar múltiples instancias de un mismo módulo bien para añadir redundancia o bien para incrementar la capacidad de procesamiento. Todo ello sin que el código de aplicación cambie. • Transparencia a la posición: la posición física de los módulos hardware es arbitraria para su direccionamiento desde el código de aplicación. • Transparencia a los fallos: si existe un fallo en un módulo hardware, gracias a la redundancia, el código de aplicación tomará directamente el resultado correcto. • Transparencia a la concurrencia: el hecho de que una tarea sea realizada por más o menos bloques es transparente para el código que la invoca. Por lo tanto, esta tesis doctoral contribuye en dos líneas diferentes. En primer lugar, con el diseño de la plataforma HiReCookie y en segundo lugar con el diseño de la arquitectura ARTICo3. Las principales contribuciones de esta tesis se resumen a continuación. • Arquitectura de la HiReCookie incluyendo: o Compatibilidad con la plataforma Cookies para incrementar las capacidades de esta. o División de la arquitectura en distintas islas de alimentación. o Implementación de los diversos modos de bajo consumo y políticas de despertado del nodo. o Creación de un archivo de configuración de la FPGA comprimido para reducir el tiempo y el consumo de la configuración inicial. • Diseño de la arquitectura reconfigurable para FPGAs basadas en RAM ARTICo3: o Modelo de computación y modos de ejecución inspirados en el modelo de CUDA pero basados en hardware reconfigurable con un número variable de bloques de hilos por cada unidad de ejecución. o Estructura para optimizar las transacciones de datos en ráfaga proporcionando datos en cascada o en paralelo a los distinto módulos incluyendo un proceso de votado por mayoría y operaciones de reducción. o Capa de abstracción entre el procesador principal que incluye el código de aplicación y los recursos asignados para las diferentes tareas. o Arquitectura de los módulos hardware reconfigurables para mantener la escalabilidad añadiendo una la interfaz para las nuevas funcionalidades con un simple acceso a una memoria RAM interna. o Caracterización online de las tareas para proporcionar información a un módulo de gestión de recursos para mejorar la operación en términos de energía y procesamiento cuando además se opera entre distintos nieles de tolerancia a fallos. El documento está dividido en dos partes principales formando un total de cinco capítulos. En primer lugar, después de motivar la necesidad de nuevas plataformas para cubrir las nuevas aplicaciones, se detalla el diseño de la plataforma HiReCookie, sus partes, las posibilidades para bajar el consumo energético y se muestran casos de uso de la plataforma así como pruebas de validación del diseño. La segunda parte del documento describe la arquitectura reconfigurable, su implementación en varias FPGAs, y pruebas de validación en términos de capacidad de procesamiento y consumo energético, incluyendo cómo estos aspectos se ven afectados por el nivel de tolerancia a fallos elegido. Los capítulos a lo largo del documento son los siguientes: El capítulo 1 analiza los principales objetivos, motivación y aspectos teóricos necesarios para seguir el resto del documento. El capítulo 2 está centrado en el diseño de la plataforma HiReCookie y sus posibilidades para disminuir el consumo de energía. El capítulo 3 describe la arquitectura reconfigurable ARTICo3. El capítulo 4 se centra en las pruebas de validación de la arquitectura usando la plataforma HiReCookie para la mayoría de los tests. Un ejemplo de aplicación es mostrado para analizar el funcionamiento de la arquitectura. El capítulo 5 concluye esta tesis doctoral comentando las conclusiones obtenidas, las contribuciones originales del trabajo y resultados y líneas futuras. ABSTRACT This PhD Thesis is framed within the field of dynamically reconfigurable embedded systems, advanced sensor networks and distributed computing. The document is centred on the study of processing solutions for high-performance autonomous distributed systems (HPADS) as well as their evolution towards High performance Computing (HPC) systems. The approach of the study is focused on both platform and processor levels to optimise critical aspects such as computing performance, energy efficiency and fault tolerance. HPADS are considered feedback systems, normally networked and/or distributed, with real-time adaptive and predictive functionality. These systems, as part of more complex systems known as Cyber-Physical Systems (CPSs), can be applied in a wide range of fields such as military, health care, manufacturing, aerospace, etc. For the design of HPADS, high levels of dependability, the definition of suitable models of computation, and the use of methodologies and tools to support scalability and complexity management, are required. The first part of the document studies the different possibilities at platform design level in the state of the art, together with description, development and validation tests of the platform proposed in this work to cope with the previously mentioned requirements. The main objectives targeted by this platform design are the following: • Study the feasibility of using SRAM-based FPGAs as the main processor of the platform in terms of energy consumption and performance for high demanding applications. • Analyse and propose energy management techniques to reduce energy consumption in every stage of the working profile of the platform. • Provide a solution with dynamic partial and wireless remote HW reconfiguration (DPR) to be able to change certain parts of the FPGA design at run time and on demand without interrupting the rest of the system. • Demonstrate the applicability of the platform in different test-bench applications. In order to select the best approach for the platform design in terms of processing alternatives, a study of the evolution of the state-of-the-art platforms is required to analyse how different architectures cope with new more demanding applications and scenarios: security, mixed-critical systems for aerospace, multimedia applications, or military environments, among others. In all these scenarios, important changes in the required processing bandwidth or the complexity of the algorithms used are provoking the migration of the platforms from single microprocessor architectures to multiprocessing and heterogeneous solutions with more instant power consumption but higher energy efficiency. Within these solutions, FPGAs and Systems on Chip including FPGA fabric and dedicated hard processors, offer a good trade of among flexibility, processing performance, energy consumption and price, when they are used in demanding applications where working conditions are very likely to vary over time and high complex algorithms are required. The platform architecture proposed in this PhD Thesis is called HiReCookie. It includes an SRAM-based FPGA as the main and only processing unit. The FPGA selected, the Xilinx Spartan-6 LX150, was at the beginning of this work the best choice in terms of amount of resources and power. Although, the power levels are the lowest of these kind of devices, they can be still very high for distributed systems that normally work powered by batteries. For that reason, it is necessary to include different energy saving possibilities to increase the usability of the platform. In order to reduce energy consumption, the platform architecture is divided into different power islands so that only those parts of the systems that are strictly needed are powered on, while the rest of the islands can be completely switched off. This allows a combination of different low power modes to decrease energy. In addition, one of the most important handicaps of SRAM-based FPGAs is that they are not alive at power up. Therefore, recovering the system from a switch-off state requires to reload the FPGA configuration from a non-volatile memory device. For that reason, this PhD Thesis also proposes a methodology to compress the FPGA configuration file in order to reduce time and energy during the initial configuration process. Although some of the requirements for the design of HPADS are already covered by the design of the HiReCookie platform, it is necessary to continue improving energy efficiency, computing performance and fault tolerance. This is only possible by exploiting all the opportunities provided by the processing architectures configured inside the FPGA. Therefore, the second part of the thesis details the design of the so called ARTICo3 FPGA architecture to enhance the already intrinsic capabilities of the FPGA. ARTICo3 is a DPR-capable bus-based virtual architecture for multiple HW acceleration in SRAM-based FPGAs. The architecture provides support for dynamic resource management in real time. In this way, by using DPR, it will be possible to change the levels of computing performance, energy consumption and fault tolerance on demand by increasing or decreasing the amount of resources used by the different tasks. Apart from the detailed design of the architecture and its implementation in different FPGA devices, different validation tests and comparisons are also shown. The main objectives targeted by this FPGA architecture are listed as follows: • Provide a method based on a multithread approach such as those offered by CUDA (Compute Unified Device Architecture) or OpenCL kernel executions, where kernels are executed in a variable number of HW accelerators without requiring application code changes. • Provide an architecture to dynamically adapt working points according to either self-measured or external parameters in terms of energy consumption, fault tolerance and computing performance. Taking advantage of DPR capabilities, the architecture must provide support for a dynamic use of resources in real time. • Exploit concurrent processing capabilities in a standard bus-based system by optimizing data transactions to and from HW accelerators. • Measure the advantage of HW acceleration as a technique to boost performance to improve processing times and save energy by reducing active times for distributed embedded systems. • Dynamically change the levels of HW redundancy to adapt fault tolerance in real time. • Provide HW abstraction from SW application design. FPGAs give the possibility of designing specific HW blocks for every required task to optimise performance while some of them include the possibility of including DPR. Apart from the possibilities provided by manufacturers, the way these HW modules are organised, addressed and multiplexed in area and time can improve computing performance and energy consumption. At the same time, fault tolerance and security techniques can also be dynamically included using DPR. However, the inherent complexity of designing new HW modules for every application is not negligible. It does not only consist of the HW description, but also the design of drivers and interfaces with the rest of the system, while the design space is widened and more complex to define and program. Even though the tools provided by the majority of manufacturers already include predefined bus interfaces, commercial IPs, and templates to ease application prototyping, it is necessary to improve these capabilities. By adding new architectures on top of them, it is possible to take advantage of parallelization and HW redundancy while providing a framework to ease the use of dynamic resource management. ARTICo3 works within a solution space where working points change at run time in a 3D space defined by three different axes: Computation, Consumption, and Fault Tolerance. Therefore, every working point is found as a trade-off solution among these three axes. By means of DPR, different accelerators can be multiplexed so that the amount of available resources for any application is virtually unlimited. Taking advantage of DPR capabilities and a novel way of transmitting data to the reconfigurable HW accelerators, it is possible to dedicate a dynamically-changing number of resources for a given task in order to either boost computing speed or adding HW redundancy and a voting process to increase fault-tolerance levels. At the same time, using an optimised amount of resources for a given task reduces energy consumption by reducing instant power or computing time. In order to keep level complexity under certain limits, it is important that HW changes are transparent for the application code. Therefore, different levels of transparency are targeted by the system: • Scalability transparency: a task must be able to expand its resources without changing the system structure or application algorithms. • Performance transparency: the system must reconfigure itself as load changes. • Replication transparency: multiple instances of the same task are loaded to increase reliability and performance. • Location transparency: resources are accessed with no knowledge of their location by the application code. • Failure transparency: task must be completed despite a failure in some components. • Concurrency transparency: different tasks will work in a concurrent way transparent to the application code. Therefore, as it can be seen, the Thesis is contributing in two different ways. First with the design of the HiReCookie platform and, second with the design of the ARTICo3 architecture. The main contributions of this PhD Thesis are then listed below: • Architecture of the HiReCookie platform including: o Compatibility of the processing layer for high performance applications with the Cookies Wireless Sensor Network platform for fast prototyping and implementation. o A division of the architecture in power islands. o All the different low-power modes. o The creation of the partial-initial bitstream together with the wake-up policies of the node. • The design of the reconfigurable architecture for SRAM FPGAs: ARTICo3: o A model of computation and execution modes inspired in CUDA but based on reconfigurable HW with a dynamic number of thread blocks per kernel. o A structure to optimise burst data transactions providing coalesced or parallel data to HW accelerators, parallel voting process and reduction operation. o The abstraction provided to the host processor with respect to the operation of the kernels in terms of the number of replicas, modes of operation, location in the reconfigurable area and addressing. o The architecture of the modules representing the thread blocks to make the system scalable by adding functional units only adding an access to a BRAM port. o The online characterization of the kernels to provide information to a scheduler or resource manager in terms of energy consumption and processing time when changing among different fault-tolerance levels, as well as if a kernel is expected to work in the memory-bounded or computing-bounded areas. The document of the Thesis is divided into two main parts with a total of five chapters. First, after motivating the need for new platforms to cover new more demanding applications, the design of the HiReCookie platform, its parts and several partial tests are detailed. The design of the platform alone does not cover all the needs of these applications. Therefore, the second part describes the architecture inside the FPGA, called ARTICo3, proposed in this PhD Thesis. The architecture and its implementation are tested in terms of energy consumption and computing performance showing different possibilities to improve fault tolerance and how this impact in energy and time of processing. Chapter 1 shows the main goals of this PhD Thesis and the technology background required to follow the rest of the document. Chapter 2 shows all the details about the design of the FPGA-based platform HiReCookie. Chapter 3 describes the ARTICo3 architecture. Chapter 4 is focused on the validation tests of the ARTICo3 architecture. An application for proof of concept is explained where typical kernels related to image processing and encryption algorithms are used. Further experimental analyses are performed using these kernels. Chapter 5 concludes the document analysing conclusions, comments about the contributions of the work, and some possible future lines for the work.

Substrate-specific regulation of the ribosome– translocon junction by N-terminal signal sequences

Amino-terminal signal sequences target nascent secretory and membrane proteins to the endoplasmic reticulum for translocation. Subsequent interactions between the signal sequence and components of the translocation machinery at the endoplasmic reticulum are thought to be important for the productive engagement of the translocon by the ribosome-nascent chain complex. However, it is not clear whether all signal sequences carry out these posttargeting steps identically, or if there are differences in the interactions directed by one signal sequence versus another. In this study, we find substantial differences in the ability of signal sequences from different substrates to mediate closure of the ribosome–translocon junction early in translocation. We also show that these differences in some cases necessitate functional coordination between the signal sequence and mature domain for faithful translocation. Accordingly, the translocation of some proteins is sensitive to replacement of their signal sequences. In a particularly dramatic example, the topology of the prion protein was found to depend highly on the choice of signal sequence used to direct its translocation. Taken together, our results reveal an unanticipated degree of substrate-specific functionality encoded in N-terminal signal sequences.

Regulation of the myeloperoxidase enhancer binding proteins Pu1, C-EBP alpha, -beta, and -delta during granulocyte-lineage specification.

We have compared the molecular architecture and function of the myeloperoxidase upstream enhancer in multipotential versus granulocyte-committed hematopoietic progenitor cells. We show that the enhancer is accessible in multipotential cell chromatin but functionally incompetent before granulocyte commitment. Multipotential cells contain both Pu1 and C-EBP alpha as enhancer-binding activities. Pu1 is unphosphorylated in both multipotential and granulocyte-committed cells but is phosphorylated in B lymphocytes, raising the possibility that differential phosphorylation may play a role in specifying its lymphoid versus myeloid functions. C-EBP alpha exists as multiple phosphorylated forms in the nucleus of both multipotential and granulocyte-committed cells. C-EBP beta is unphosphorylated and cytoplasmically localized in multipotential cells but exists as a phosphorylated nuclear enhancer-binding activity in granulocyte-committed cells. Granulocyte colony-stimulating factor-induced granulocytic differentiation of multipotential progenitor cells results in activation of C-EBP delta expression and functional recruitment of C-EBP delta and C-EBP beta to the nucleus. Our results implicate Pu1 and the C-EBP family as critical regulators of myeloperoxidase gene expression and are consistent with a model in which a temporal exchange of C-EBP isoforms at the myeloperoxidase enhancer mediates the transition from a primed state in multipotential cells to a transcriptionally active configuration in promyelocytes.

Extracellular pH regulation in microdomains of colonic crypts: effects of short-chain fatty acids.

It has been suggested that transepithelial gradients of short-chain fatty acids (SCFAs; the major anions in the colonic lumen) generate pH gradients across the colonic epithelium. Quantitative confocal microscopy was used to study extracellular pH in mouse distal colon with intact epithelial architecture, by superfusing tissue with carboxy SNARF-1 (a pH-sensitive fluorescent dye). Results demonstrate extracellular pH regulation in two separate microdomains surrounding colonic crypts: the crypt lumen and the subepithelial tissue adjacent to crypt colonocytes. Apical superfusion with (i) a poorly metabolized SCFA (isobutyrate), (ii) an avidly metabolized SCFA (n-butyrate), or (iii) a physiologic mixture of acetate/propionate/n-butyrate produced similar results: alkalinization of the crypt lumen and acidification of subepithelial tissue. Effects were (i) dependent on the presence and orientation of a transepithelial SCFA gradient, (ii) not observed with gluconate substitution, and (iii) required activation of sustained vectorial acid/base transport by SCFAs. Results suggest that the crypt lumen functions as a pH microdomain due to slow mixing with bulk superfusates and that crypts contribute significant buffering capacity to the lumen. In conclusion, physiologic SCFA gradients cause polarized extracellular pH regulation because epithelial architecture and vectorial transport synergize to establish regulated microenvironments.

International financial regulation: A role for the Eurozone? EU Diplomacy Paper 08/2012, October 2012

The deepest financial crisis to strike the global economy since the Great Depression has unceremoniously called into question the very foundations of the Western economic model. The liberalisation of capital flows and the growing internationalisation of financial markets outpaced global regulatory and supervisory efforts. The repercussions of the financial crisis have given new dynamism to the reform of financial regulation both globally and within the European Union (EU). The Eurozone, by way of its own failings, has emerged as a stronger conceptual and legitimate entity since the onset of the crisis, but to what extent does this equate to a greater external role, in particular in the reform of international financial regulation? This paper argues that the Eurozone is currently not in a position to play an important role in the reform of international financial regulation, as it is a weak actor in the context of the EU financial architecture, which is still largely characterised by differing national regimes, a prevailing influence from the UK and fragmented external representation. The key finding from this study is that internal tensions in the EU are at the very heart of the Eurozone’s difficulties in playing a role in the reform of international financial regulation. Surmounting these tensions is a pre-requisite for the Eurozone if it is to overcome its structural weakness in international financial politics. However, the implications of such evolutions to the Eurozone, as an entity, and to European integration are far-reaching.

Institutional Moral Hazard in the Multi-tiered Regulation of Unemployment and Social Assistance Benefits. CEPS Special Report No. 137/April 2016 Wednesday, 27 April 2016

This paper studies eight countries in which the regulation of unemployment benefits and related benefits and the concomitant activation of unemployed individuals has a multi-tiered architecture. It assesses their experiences and tries to understand possible problems of ‘institutional moral hazard’ that may emerge in the context of a hypothetical European Unemployment Benefit Scheme.

Should energy efficiency be traded off for other product attributes? : an analysis of air-conditioner regulation in Japan

This paper examines the functioning of energy efficiency standards and labeling policies for air conditioners in Japan. The results of our empirical analysis suggest that consumers respond more to label information, which benchmarks the energy efficiency performance of each product to a pre-specified target, than to direct performance measures. This finding provides justification for the setting, and regular updating, of target standards as well as their use in calculating relative performance measures. We also find, through graphical analysis, that air conditioner manufacturers face a tradeoff between energy efficiency and product compactness when they develop their products. This tradeoff, combined with the semi-regular upward revision of minimum energy efficiency standards, has led to the growth in indoor unit size of air conditioners in recent years. In the face of this phenomenon, regulatory rules were revised so that manufacturers could adhere to less stringent standards if the indoor unit size of their product remains below a certain size. Our demand estimates provide no evidence that larger indoor unit size causes disutility to consumers. It is therefore possible that the regulatory change was not warranted from a consumer welfare point of view.

Genome-wide analysis of mammalian promoter architecture and evolution

Mammalian promoters can be separated into two classes, conserved TATA box-enriched promoters, which initiate at a welldefined site, and more plastic, broad and evolvable CpG-rich promoters. We have sequenced tags corresponding to several hundred thousand transcription start sites (TSSs) in the mouse and human genomes, allowing precise analysis of the sequence architecture and evolution of distinct promoter classes. Different tissues and families of genes differentially use distinct types of promoters. Our tagging methods allow quantitative analysis of promoter usage in different tissues and show that differentially regulated alternative TSSs are a common feature in protein-coding genes and commonly generate alternative N termini. Among the TSSs, we identified new start sites associated with the majority of exons and with 3' UTRs. These data permit genome-scale identification of tissue-specific promoters and analysis of the cis-acting elements associated with them.