A central role for heme iron in colon carcinogenesis associated with red meat intake

Epidemiology shows that red and processed meat intake is associated with an increased risk of colorectal cancer. Heme iron, heterocyclic amines and endogenous N-nitroso compounds (NOC) are proposed to explain this effect, but their relative contribution is unknown. Our study aimed at determining, at nutritional doses, which is the main factor involved and proposing a mechanism of cancer promotion by red meat. The relative part of heme iron (1% in diet), heterocyclic amines (PhIP+MeIQx, 50+25 μg/kg in diet) and NOC (induced by NaNO2+NaNO3 0.17+0.23 g/l of drinking water) was determined by a factorial design and preneoplastic endpoints in chemically-induced rats and validated on tumors in Min mice. The molecular mechanisms (genotoxicity, cytotoxicity) were analyzed in vitro in normal and Apc- deficient cell lines and confirmed on colon mucosa. Heme iron increased the number of preneoplastic lesions but dietary heterocyclic amines and NOC had no effect on carcinogenesis in rats. Dietary hemoglobin increased tumor load in Min mice (control diet: 67±39 mm2; 2,5% hemoglobin diet: 114±47 mm2, p=0.004). In vitro, fecal water from rats given hemoglobin was rich in aldehydes and was cytotoxic to normal cells, but not to premalignant cells. The aldehydes 4-hydroxynonenal and 4-hydroxyhexenal were more toxic to normal versus mutated cells and were only genotoxic to normal cells. Genotoxicity was also observed in colon mucosa of mice given hemoglobin. These results highlight the role of heme iron in the promotion of colon cancer by red meat and suggest that heme iron could initiate carcinogenesis through lipid peroxidation.

Redes-em-chip de baixo custo

Com as recentes tecnologias de fabricação é possível integrar milhões de transistores em um único chip, permitindo a criação dos chamados System-on-Chip (SoCs), que integram em um único chip um grande número de componentes (tipicamente blocos reutilizáveis conhecidos por núcleos). Quanto mais complexos forem estes sistemas, melhores técnicas de projeto serão necessárias para também reduzir o tempo e custo do projeto. Uma destas técnicas, chamada de Network-on-Chip (NoC), permite melhorar a performance da comunicação entre os núcleos e, ao mesmo tempo, fornecer uma plataforma de comunicação escalável e que pode ser reutilizada para um grande número de sistemas. Uma NoC pode ser definida como uma estrutura de roteadores e canais ponto-a-ponto que interconectam os núcleos de um sistema, provendo o suporte de comunicação entre eles. Os dados são transmitidos pela rede na forma de mensagens, que podem ser divididas em unidades menores chamadas de pacote. Uma das desvantagens desta plataforma de comunicação é o impacto na área do sistema causado pelos roteadores. Dentro deste contexto, este trabalho apresenta uma arquitetura de roteador de baixo custo, com o objetivo de permitir o uso de NoCs em sistemas onde a área do roteador representará um grande impacto no custo do sistema. A arquitetura deste roteador, chamado de Tonga, é baseada em um roteador chamado RASoC, um soft-core para SoCs. Nesta dissertação será apresentada também uma rede heterogênea, baseada na rede SoCIN, e composta por dois tipos de roteadores – RASoC e Tonga. Estes roteadores visam diferentes objetivos: Rasoc alcança uma maior performance comparada ao Tonga, mas ocupa área consideravelmente maior. Potencialmente, uma NoC heterogênea otimizada pode ser desenvolvida combinando estes roteadores, procurando o melhor compromisso entre área e latência. Os modelos desenvolvidos permitem a estimativa de área e do desempenho das arquiteturas de comunicação propostas e são apresentados resultados de performance para algumas aplicações.

Definições para o resultado de enfermagem comportamento de prevenção de quedas: uma revisão integrativa

Devido à necessidade de mensurar o risco de quedas em concordância à linguagem padronizada de enfermagem, foi selecionado o resultado de enfermagem Comportamento para Prevenção de Quedas da Nursing Outcomes Classification (NOC), com objetivo de identificar evidências sobre seus elementos, mensuração, comparação com indicadores existentes e construir definições constitutivas. Foi efetuada revisão integrativa entre abril e novembro de 2009, mediante identificação da questão, estabelecimento de critérios de inclusão/exclusão, extração das informações, avaliação, interpretação e síntese. Destacaram-se pesquisas transversais e perspectivas de especialistas. Os indicadores Uso de recursos de correção da visão e Uso de sapatos amarrados e do tamanho adequado foram considerados insuficientes para avaliar fatores de risco como déficits sensoriais e roupas/calçados inadequados. Percebe-se que algumas definições precisam ser melhor desenvolvidas e que esse resultado de enfermagem merece refinamento sobretudo referente aos indicadores. Foram identificados 22 indicadores e definições foram propostas baseadas nas evidências da literatura

Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys

It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it

Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys

The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The results from simulation confirm the viability of development of IPNoSys system. They showed that is possible to perform application described in packages, sequentially or parallelly, without interruptions caused by deadlock, and also showed that the execution time of IPNoSys is more efficient than the STORM platform

Sistema operacional e biblioteca de funções para plataformas MPSOC: um estudo de caso para simuladores de reservatórios

The increasingly request for processing power during last years has pushed integrated circuit industry to look for ways of providing even more processing power with less heat dissipation, power consumption, and chip area. This goal has been achieved increasing the circuit clock, but since there are physical limits of this approach a new solution emerged as the multiprocessor system on chip (MPSoC). This approach demands new tools and basic software infrastructure to take advantage of the inherent parallelism of these architectures. The oil exploration industry has one of its firsts activities the project decision on exploring oil fields, those decisions are aided by reservoir simulations demanding high processing power, the MPSoC may offer greater performance if its parallelism can be well used. This work presents a proposal of a micro-kernel operating system and auxiliary libraries aimed to the STORM MPSoC platform analyzing its influence on the problem of reservoir simulation

Avaliação da execução de aplicações orientadas à dados na arquitetura de redes em chip IPNoSys

The increasing complexity of integrated circuits has boosted the development of communications architectures like Networks-on-Chip (NoCs), as an architecture; alternative for interconnection of Systems-on-Chip (SoC). Networks-on-Chip complain for component reuse, parallelism and scalability, enhancing reusability in projects of dedicated applications. In the literature, lots of proposals have been made, suggesting different configurations for networks-on-chip architectures. Among all networks-on-chip considered, the architecture of IPNoSys is a non conventional one, since it allows the execution of operations, while the communication process is performed. This study aims to evaluate the execution of data-flow based applications on IPNoSys, focusing on their adaptation against the design constraints. Data-flow based applications are characterized by the flowing of continuous stream of data, on which operations are executed. We expect that these type of applications can be improved when running on IPNoSys, because they have a programming model similar to the execution model of this network. By observing the behavior of these applications when running on IPNoSys, were performed changes in the execution model of the network IPNoSys, allowing the implementation of an instruction level parallelism. For these purposes, analysis of the implementations of dataflow applications were performed and compared

Implementação da técnica de software pipelining na rede em chip IPNoSyS

Alongside the advances of technologies, embedded systems are increasingly present in our everyday. Due to increasing demand for functionalities, many tasks are split among processors, requiring more efficient communication architectures, such as networks on chip (NoC). The NoCs are structures that have routers with channel point-to-point interconnect the cores of system on chip (SoC), providing communication. There are several networks on chip in the literature, each with its specific characteristics. Among these, for this work was chosen the Integrated Processing System NoC (IPNoSyS) as a network on chip with different characteristics compared to general NoCs, because their routing components also accumulate processing function, ie, units have functional able to execute instructions. With this new model, packets are processed and routed by the router architecture. This work aims at improving the performance of applications that have repetition, since these applications spend more time in their execution, which occurs through repeated execution of his instructions. Thus, this work proposes to optimize the runtime of these structures by employing a technique of instruction-level parallelism, in order to optimize the resources offered by the architecture. The applications are tested on a dedicated simulator and the results compared with the original version of the architecture, which in turn, implements only packet level parallelism

A petri net based timing model for hardware/software co-design of digital systems

We have recently proposed an extension to Petri nets in order to be able to directly deal with all aspects of embedded digital systems. This extension is meant to be used as an internal model of our co-design environment. After analyzing relevant related work, and presenting a short introduction to our extension as a background material, we describe the details of the timing model we use in our approach, which is mainly based in Merlin's time model. We conclude the paper by discussing an example of its usage. © 2004 IEEE.

Efeitos ansiogênicos do óxido nítrico no córtex pre-frontal medial de camundongos

Medo e a ansiedade são emoções que têm origem nas reações de defesa que os animais exibem diante de ameaças que podem comprometer sua integridade física ou a própria sobrevivência, tais como confrontos com o predador ou com animais da mesma espécie. Em se tratando da espécie humana, estas respostas defensivas eliciadas representariam a ocorrência de transtornos de ansiedade e, a busca por sua compreensão, resultou no desenvolvimento de modelos animais de ansiedade, dentre os quais se destaca o labirinto em cruz elevado (LCE) que é baseado na aversão natural de roedores a espaços abertos. Com relação aos substratos neurais envolvidos nestas manifestações, cabe destacar a matéria cinzenta periaquedutal bem como estruturas prosencefálicas, como o córtex pré-frontal (CPFm), uma estrutura límbica que tem sido frequentemente descrita como relevante na neurobiologia da ansiedade. O óxido nítrico (NO) tem sido investigado em diferentes estruturas cerebrais de roedores nas quais foram evidenciadas respostas pró-aversivas. Sendo o CPFm uma estrutura que contém neurônios nitrérgicos, este estudo teve o objetivo de investigar o efeito da facilitação nitrérgica através da injeção intra-CPFm de um doador de NO, o NOC-9 [6-(Hidroxi-1-metil-2-nitrosohidrazino)-N-metil-1-hexanamina], sobre o comportamento de camundongos expostos ao labirinto em cruz elevado (LCE). Métodos e Resultados: Camundongos Suíços machos (25-35g, n = 53) receberam implante de cânula guia no CPFm. Cinco dias após, os animais receberam microinjeção de veículo ou NOC-9 nas doses de (1,875 nmol; 18,75 nmol; 37,5 nmol ou 75nmol) e, após cinco minutos, foram expostos... (Resumo completo, clicar acesso eletrônico abaixo)

Contrasting effects of nitric oxide and corticotropin-releasing factor within the dorsal periaqueductal gray on defensive behavior and nociception in mice

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

High-resolution stratigraphy of Central and Southern Adriatic Quaternary deposits of sub-Milankovian climate change on Mediterranean circulation

This volume is a collection of the work done in a three years-lasting PhD, focused in the analysis of Central and Southern Adriatic marine sediments, deriving from the collection of a borehole and many cores, achieved thanks to the good seismic-stratigraphic knowledge of the study area. The work was made out within European projects EC-EURODELTA (coordinated by Fabio Trincardi, ISMAR-CNR), EC-EUROSTRATAFORM (coordinated by Phil P. E. Weaver, NOC, UK), and PROMESS1 (coordinated by Serge Bernè, IFREMER, France). The analysed sedimentary successions presented highly expanded stratigraphic intervals, particularly for the last 400 kyr, 60 kyr and 6 kyr BP. These three different time-intervals resulted in a tri-partition of the PhD thesis. The study consisted of the analysis of planktic and benthic foraminifers’ assemblages (more than 560 samples analysed), as well as in preparing the material for oxygen and carbon stable isotope analyses, and interpreting and discussing the obtained dataset. The chronologic framework of the last 400 kyr was achieved for borehole PRAD1-2 (within the work-package WP6 of PROMESS1 project), collected in 186.5 m water depth. The proposed chronology derives from a multi-disciplinary approach, consisting of the integration of numerous and independent proxies, some of which analysed by other specialists within the project. The final framework based on: micropaleontology (calcareous nannofossils and foraminifers’ bioevents), climatic cyclicity (foraminifers’ assemblages), geochemistry (oxygen stable isotope, made out on planktic and benthic records), paleomagnetism, radiometric ages (14C AMS), teprhochronology, identification of sapropel-equivalent levels (Se). It’s worth to note the good consistency between the oxygen stable isotope curve obtained for borehole PRAD1-2 and other deeper Mediterranean records. The studied proxies allowed the recognition of all the isotopic intervals from MIS10 to MIS1 in PRAD1-2 record, and the base of the borehole has been ascribed to the early MIS11. Glacial and interglacial intervals identified in the Central Adriatic record have been analysed in detail for the paleo-environmental reconstruction, as well. For instance, glacial stages MIS6, MIS8 and MIS10 present peculiar foraminifers’ assemblages, composed by benthic species typical of polar regions and no longer living in the Central Adriatic nowadays. Moreover, a deepening trend in the paleo-bathymetry during glacial intervals was observed, from MIS10 (inner-shelf environment) to MIS4 (mid-shelf environment).Ten sapropel-equivalent levels have been recognised in PRAD1-2 Central Adriatic record. They showed different planktic foraminifers’ assemblages, which allowed the first distinction of events occurred during warm-climate (Se5, Se7), cold-climate (Se4, Se6 and Se8) and temperate-intermediate-climate (Se1, Se3, Se9, Se’, Se10) conditions, consistently with literature. Cold-climate sapropel equivalents are characterised by the absence of an oligotrophic phase, whereas warm-temeprate-climate sapropel equivalents present both the oligotrophic and the eutrophic phases (except for Se1). Sea floor conditions vary, according to benthic foraminifers’ assemblages, from relatively well oxygenated (Se1, Se3), to dysoxic (Se9, Se’, Se10), to highly dysoxic (Se4, Se6, Se8) to events during which benthic foraminifers are absent (Se5, Se7). These two latter levels are also characterised by the lamination of the sediment, feature never observed in literature in such shallow records. The enhanced stratification of the water column during the events Se8, Se7, Se6, Se5, Se4, and the concurring strong dilution of shallow water, pointed out by the isotope record, lead to the hypothesis of a period of intense precipitation in the Central Adriatic region, possibly due to a northward shift of the African Monsoon. Finally, the expression of Central Adriatic PRAD1-2 Se5 equivalent was compared with the same event, as registered in other Eastern Mediterranean areas. The sequence of substantially the same planktic foraminifers’ bioevents has been consistently recognised, indicating a similar evolution of the water column all over the Eastern Mediterranean; yet, the synchronism of these events cannot be demonstrated. A high resolution analysis of late Holocene (last 6000 years BP) climate change was carried out for the Adriatic area, through the recognition of planktic and benthic foraminifers’ bioevents. In particular, peaks of planktic Globigerinoides sacculifer (four during the last 5500 years BP in the most expanded core) have been interpreted, based on the ecological requirements of this species, as warm-climate, arid intervals, correspondent to periods of relative climatic optimum, such as, for instance, the Medieval Warm Period, the Roman Age, the Late Bronze Age and the Copper Age. Consequently, the minima in the abundance of this biomarker could correspond to relatively cooler and more rainy periods. These conclusions are in good agreement with the isotopic and the pollen data. The Last Occurrence (LO) of G. sacculifer has been dated in this work at an average age of 550 years BP, and it is the best bioevent approximating the base of the Little Ice Age in the Adriatic. Recent literature reports the same bioevent in the Levantine Basin, showing a rather consistent age. Therefore, the LO of G. sacculifer has the potential to be extended to all the Eastern Mediterranean. Within the Little Ice Age, benthic foraminifer V. complanata shows two distinct peaks in the shallower Adriatic cores analysed, collected hundred kilometres apart, inside the mud belt environment. Based on the ecological requirements of this species, these two peaks have been interpreted as the more intense (cold and rainy) oscillations inside the LIA. The chronologic framework of the analysed cores is robust, being based on several range-finding 14C AMS ages, on estimates of the secular variation of the magnetic field, on geochemical estimates of the activity depth of 210Pb short-lived radionuclide (for the core-top ages), and is in good agreement with tephrochronologic, pollen and foraminiferal data. The intra-holocenic climate oscillations find out in the Adriatic have been compared with those pointed out in literature from other records of the Northern Hemisphere, and the chronologic constraint seems quite good. Finally, the sedimentary successions analysed allowed the review and the update of the foraminifers’ ecobiostratigraphy available from literature for the Adriatic region, thanks to the achievement of 16 ecobiozones for the last 60 kyr BP. Some bioevents are restricted to the Central Adriatic (for instance the LO of benthic Hyalinea balthica , approximating the MIS3/MIS2 boundary), others occur all over the Adriatic basin (for instance the LO of planktic Globorotalia inflata during MIS3, individuating Dansgaard-Oeschger cycle 8 (Denekamp)).

Interconnection systems for highly integrated computation devices

The sustained demand for faster,more powerful chips has beenmet by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SOC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MPSOC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NOCS) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the on-chip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation focuses on all of the above points, by describing a NoC architectural implementation called ×pipes; a NoC simulation environment within a cycle-accurate MPSoC emulator called MPARM; a NoC design flow consisting of a front-end tool for optimal NoC instantiation, called SunFloor, and a set of back-end facilities for the study of NoC physical implementations. This dissertation proves the viability of NoCs for current and upcoming designs, by outlining their advantages (alongwith a fewtradeoffs) and by providing a full NoC implementation framework. It also presents some examples of additional extensions of NoCs, allowing e.g. for increased fault tolerance, and outlines where NoCsmay find further application scenarios, such as in stacked chips.

Design and Performance Evaluation of Network-on-Chip Communication Protocols and Architectures

The scale down of transistor technology allows microelectronics manufacturers such as Intel and IBM to build always more sophisticated systems on a single microchip. The classical interconnection solutions based on shared buses or direct connections between the modules of the chip are becoming obsolete as they struggle to sustain the increasing tight bandwidth and latency constraints that these systems demand. The most promising solution for the future chip interconnects are the Networks on Chip (NoC). NoCs are network composed by routers and channels used to inter- connect the different components installed on the single microchip. Examples of advanced processors based on NoC interconnects are the IBM Cell processor, composed by eight CPUs that is installed on the Sony Playstation III and the Intel Teraflops pro ject composed by 80 independent (simple) microprocessors. On chip integration is becoming popular not only in the Chip Multi Processor (CMP) research area but also in the wider and more heterogeneous world of Systems on Chip (SoC). SoC comprehend all the electronic devices that surround us such as cell-phones, smart-phones, house embedded systems, automotive systems, set-top boxes etc... SoC manufacturers such as ST Microelectronics , Samsung, Philips and also Universities such as Bologna University, M.I.T., Berkeley and more are all proposing proprietary frameworks based on NoC interconnects. These frameworks help engineers in the switch of design methodology and speed up the development of new NoC-based systems on chip. In this Thesis we propose an introduction of CMP and SoC interconnection networks. Then focusing on SoC systems we propose: • a detailed analysis based on simulation of the Spidergon NoC, a ST Microelectronics solution for SoC interconnects. The Spidergon NoC differs from many classical solutions inherited from the parallel computing world. Here we propose a detailed analysis of this NoC topology and routing algorithms. Furthermore we propose aEqualized a new routing algorithm designed to optimize the use of the resources of the network while also increasing its performance; • a methodology flow based on modified publicly available tools that combined can be used to design, model and analyze any kind of System on Chip; • a detailed analysis of a ST Microelectronics-proprietary transport-level protocol that the author of this Thesis helped developing; • a simulation-based comprehensive comparison of different network interface designs proposed by the author and the researchers at AST lab, in order to integrate shared-memory and message-passing based components on a single System on Chip; • a powerful and flexible solution to address the time closure exception issue in the design of synchronous Networks on Chip. Our solution is based on relay stations repeaters and allows to reduce the power and area demands of NoC interconnects while also reducing its buffer needs; • a solution to simplify the design of the NoC by also increasing their performance and reducing their power and area consumption. We propose to replace complex and slow virtual channel-based routers with multiple and flexible small Multi Plane ones. This solution allows us to reduce the area and power dissipation of any NoC while also increasing its performance especially when the resources are reduced. This Thesis has been written in collaboration with the Advanced System Technology laboratory in Grenoble France, and the Computer Science Department at Columbia University in the city of New York.