Patients with biallelic mutations in the chloride channel gene CLCNKB: long-term management and outcome

BACKGROUND: Little information on the management and long-term follow-up of patients with biallelic mutations in the chloride channel gene CLCNKB is available. METHODS: Long-term follow-up was evaluated from 5.0 to 24 years (median, 14 years) after diagnosis in 13 patients with homozygous (n = 10) or compound heterozygous (n = 3) mutations. RESULTS: Medical treatment at last follow-up control included supplementation with potassium in 12 patients and sodium in 2 patients and medical treatment with indomethacin in 9 patients. At the end of follow-up, body height was 2.0 standard deviation score or less in 6 patients; 2 of these patients had growth hormone deficiency. Body weight (standard deviation score in 6 patients) significantly increased (P < 0.05) at the end of follow-up in comparison to values at diagnosis. Nonpostural persistent proteinuria was present in 6 patients, and 4 patients had a glomerular filtration rate less than 75 mL/min/1.73 m(2) (<1.25 mL/s). CONCLUSION: These data show that some patients with biallelic mutations in the chloride channel gene CLCNKB tend to present with pathological proteinuria and impaired kidney function after a median follow-up of 14 years, and growth retardation is common and sometimes related to growth hormone deficiency in these patients.

Performance Analysis and Comparison between Legacy-PSM and U-APSD

This paper evaluates the performance of the most popular power saving mechanisms defined in the IEEE 802.11 standard, namely the Power Save Mode (Legacy-PSM) and the Unscheduled Automatic Power Save Delivery (U-APSD). The assessment comprises a detailed study concerning energy efficiency and capability to guarantee the required Quality of Service (QoS) for a certain application. The results, obtained in the OMNeT++ simulator, showed that U-APSD is more energy efficient than Legacy-PSM without compromising the end-to- end delay. Both U-APSD and Legacy-PSM revealed capability to guarantee the application QoS requirements in all the studied scenarios. However, unlike U-APSD, when Legacy-PSM is used in the presence of QoS demanding applications, all the stations connected to the network through the same access point will consume noticeable additional energy.

Great Barrier Reef coral element/Ca and stable isotope data and U-Th ages from IODP Expedition 325

Tropical south-western Pacific temperatures are of vital importance to the Great Barrier Reef (GBR), but the role of sea surface temperatures (SSTs) in the growth of the GBR since the Last Glacial Maximum remains largely unknown. Here we present records of Sr/Ca and d18O for Last Glacial Maximum and deglacial corals that show a considerably steeper meridional SST gradient than the present day in the central GBR. We find a 1-2 °C larger temperature decrease between 17° and 20°S about 20,000 to 13,000 years ago. The result is best explained by the northward expansion of cooler subtropical waters due to a weakening of the South Pacific gyre and East Australian Current. Our findings indicate that the GBR experienced substantial meridional temperature change during the last deglaciation, and serve to explain anomalous deglacial drying of northeastern Australia. Overall, the GBR developed through significant SST change and may be more resilient than previously thought.

The prevalence of childhood obesity in primary school children in urban Khon Kaen, Northeast Thailand

Childhood obesity is a serious public health problem because of its strong association with adulthood obesity and the related adverse health consequences. The published literature indicates a rising prevalence of childhood obesity in both developed and developing countries. However no data exists on the prevalence in Northeast Thailand, one of the poorest regions of the country and one that has experienced a recent economic transition. The objective of this study was to estimate the prevalence of obesity in seven to nine year old children in urban Khon Kaen, Northeast Thailand. A cross-sectional school based survey was conducted to determine the prevalence of obesity in children of urban Khon Kaen, Thailand. Multi-staged cluster sampling was used to select 12 school clusters of 72 children each between the ages of 7 and 9 years, in primary school grades 1, 2 and 3 from government, private and demonstration schools. A total of 864 seven to nine year old school children were studied. Anthropometric measurements of standing height and weight were taken for all subjects to the nearest tenth of a centimetre and tenth of a kilogram respectively. Childhood obesity was defined as a weight-for-height Z-score above 2.0 standard deviations of the National Center for Health Statistics/World Health Organisation reference population median. The prevalence of childhood obesity was 10.8% (95% CI: 7.6, 13.9). Obesity was significantly more prevalent in boys than girls. The biggest difference was observed between the three school types, with the highest prevalence of obesity found at teacher training demonstration schools and the lowest at the government schools. This study provides the first data on childhood obesity prevalence in Northeast Thailand. The prevalence of 10.8 per cent is lower than that found in two other urban areas of Thailand but slightly higher than expected for this relatively poor region. If this prevalence rate increases, as observed in other countries in economic transition, the incidence of non-communicable diseases associated with obesity is also likely to increase, thus raising cause for concern and reason for intervention to both control and prevent obesity during childhood.

Testing of Interposer-Based 2.5D Integrated Circuits

The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.

Implementing a structural continuity constraint and a halting method for the topology optimization of energy absorbers

This study investigates topology optimization of energy absorbing structures in which material damage is accounted for in the optimization process. The optimization objective is to design the lightest structures that are able to absorb the required mechanical energy. A structural continuity constraint check is introduced that is able to detect when no feasible load path remains in the finite element model, usually as a result of large scale fracture. This assures that designs do not fail when loaded under the conditions prescribed in the design requirements. This continuity constraint check is automated and requires no intervention from the analyst once the optimization process is initiated. Consequently, the optimization algorithm proceeds towards evolving an energy absorbing structure with the minimum structural mass that is not susceptible to global structural failure. A method is also introduced to determine when the optimization process should halt. The method identifies when the optimization method has plateaued and is no longer likely to provide improved designs if continued for further iterations. This provides the designer with a rational method to determine the necessary time to run the optimization and avoid wasting computational resources on unnecessary iterations. A case study is presented to demonstrate the use of this method.

Evaluation of Community-led Complementary Feeding and Learning Sessions

Thesis (Master's)--University of Washington, 2016-08

An IEEE 802.15.4 protocol implementation (in nesC/TinyOS): reference guide v1.0

This technical report is to provide a reference guide to the implementation of the IEEE 802.15.4 protocol in nesC/TinyOS for the MICAz motes. The implementation is provided as a tool that can be used to implement, test and evaluate the current functionalities defined in the protocol standard as well as to enable the development of functionalities not yet implemented and new add-ons to the protocol.

An Explicit GTS allocation algorithm for IEEE 802.15.4

The IEEE 802.15.4 standard provides appealing features to simultaneously support real-time and non realtime traffic, but it is only capable of supporting real-time communications from at most seven devices. Additionally, it cannot guarantee delay bounds lower than the superframe duration. Motivated by this problem, in this paper we propose an Explicit Guaranteed time slot Sharing and Allocation scheme (EGSA) for beacon-enabled IEEE 802.15.4 networks. This scheme is capable of providing tighter delay bounds for real-time communications by splitting the Contention Free access Period (CFP) into smaller mini time slots and by means of a new guaranteed bandwidth allocation scheme for a set of devices with periodic messages. At the same the novel bandwidth allocation scheme can maximize the duration of the CFP for non real-time communications. Performance analysis results show that the EGSA scheme works efficiently and outperforms competitor schemes both in terms of guaranteed delay and bandwidth utilization.

A time division beacon scheduling mechanism for IEEE 802.15.4/Zigbee cluster-tree wireless sensor networks

While the IEEE 802.15.4/Zigbee protocol stack is being considered as a promising technology for low-cost low-power Wireless Sensor Networks (WSNs), several issues in the standard specifications are still open. One of those ambiguous issues is how to build a synchronized multi-hop cluster-tree network, which is quite suitable for ensuring QoS support in WSNs. In fact, the current IEEE 802.15.4/Zigbee specifications restrict the synchronization in the beacon-enabled mode (by the generation of periodic beacon frames) to star-based networks, while it supports multi-hop networking using the peer-to-peer mesh topology, but with no synchronization. Even though both specifications mention the possible use of cluster-tree topologies, which combine multihop and synchronization features, the description on how to effectively construct such a network topology is missing. This paper tackles this problem, unveils the ambiguities regarding the use of the cluster-tree topology and proposes a synchronization mechanism based on Time Division Beacon Scheduling to construct cluster-tree WSNs. We also propose a methodology for an efficient duty cycle management in each router (cluster-head) of a cluster-tree WSN that ensures the fairest use of bandwidth resources. The feasibility of the proposal is clearly demonstrated through an experimental test bed based on our own implementation of the IEEE 802.15.4/Zigbee protocol.

i-GAME: an implicit GTS allocation mechanism in IEEE 802.15.4 for time-sensitive wireless sensor networks

The IEEE 802.15.4 Medium Access Control (MAC) protocol is an enabling technology for time sensitive wireless sensor networks thanks to its Guaranteed-Time Slot (GTS) mechanism in the beacon-enabled mode. However, the protocol only supports explicit GTS allocation, i.e. a node allocates a number of time slots in each superframe for exclusive use. The limitation of this explicit GTS allocation is that GTS resources may quickly disappear, since a maximum of seven GTSs can be allocated in each superframe, preventing other nodes to benefit from guaranteed service. Moreover, the GTSs may be only partially used, resulting in wasted bandwidth. To overcome these limitations, this paper proposes i-GAME, an implicit GTS Allocation Mechanism in beacon-enabled IEEE 802.15.4 networks. The allocation is based on implicit GTS allocation requests, taking into account the traffic specifications and the delay requirements of the flows. The i-GAME approach enables the use of a GTS by multiple nodes, while all their (delay, bandwidth) requirements are still satisfied. For that purpose, we propose an admission control algorithm that enables to decide whether to accept a new GTS allocation request or not, based not only on the remaining time slots, but also on the traffic specifications of the flows, their delay requirements and the available bandwidth resources. We show that our proposal improves the bandwidth utilization compared to the explicit allocation used in the IEEE 802.15.4 protocol standard. We also present some practical considerations for the implementation of i-GAME, ensuring backward compatibility with the IEEE 801.5.4 standard with only minor add-ons.

A comprehensive simulation study of slotted CSMA/CA for IEEE 802.15.4 wireless sensor networks

In this paper, we analyze the performance limits of the slotted CSMA/CA mechanism of IEEE 802.15.4 in the beacon-enabled mode for broadcast transmissions in WSNs. The motivation for evaluating the beacon-enabled mode is due to its flexibility for WSN applications as compared to the non-beacon enabled mode. Our analysis is based on an accurate simulation model of the slotted CSMA/CA mechanism on top of a realistic physical layer, with respect to the IEEE 802.15.4 standard specification. The performance of the slotted CSMA/CA is evaluated and analyzed for different network settings to understand the impact of the protocol attributes (superframe order, beacon order and backoff exponent) on the network performance, namely in terms of throughput (S), average delay (D) and probability of success (Ps). We introduce the concept of utility (U) as a combination of two or more metrics, to determine the best offered load range for an optimal behavior of the network. We show that the optimal network performance using slotted CSMA/CA occurs in the range of 35% to 60% with respect to an utility function proportional to the network throughput (S) divided by the average delay (D).

Affymetrix Whole-Transcript Human Gene 1.0 ST array is highly concordant with standard 3' expression arrays.

The recently released Affymetrix Human Gene 1.0 ST array has two major differences compared with standard 3' based arrays: (i) it interrogates the entire mRNA transcript, and (ii) it uses DNA targets. To assess the impact of these differences on array performance, we performed a series of comparative hybridizations between the Human Gene 1.0 ST and the Affymetrix HG-U133 Plus 2.0 and the Illumina HumanRef-8 BeadChip arrays. Additionally, both RNA and DNA targets were hybridized on HG-U133 Plus 2.0 arrays. The results show that the overall reproducibility of the Gene 1.0 ST array is best. When looking only at the high intensity probes, the reproducibility of the Gene 1.0 ST array and the Illumina BeadChip array is equally good. Concordance of array results was assessed using different inter-platform mappings. Agreements are best between the two labeling protocols using HG-U133 Plus 2.0 array. The Gene 1.0 ST array is most concordant with the HG-U133 array hybridized with cDNA targets. This may reflect the impact of the target type. Overall, the high degree of correspondence provides strong evidence for the reliability of the Gene 1.0 ST array.