825 resultados para Higly Efficient


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We focus on large-scale and dense deeply embedded systems where, due to the large amount of information generated by all nodes, even simple aggregate computations such as the minimum value (MIN) of the sensor readings become notoriously expensive to obtain. Recent research has exploited a dominance-based medium access control(MAC) protocol, the CAN bus, for computing aggregated quantities in wired systems. For example, MIN can be computed efficiently and an interpolation function which approximates sensor data in an area can be obtained efficiently as well. Dominance-based MAC protocols have recently been proposed for wireless channels and these protocols can be expected to be used for achieving highly scalable aggregate computations in wireless systems. But no experimental demonstration is currently available in the research literature. In this paper, we demonstrate that highly scalable aggregate computations in wireless networks are possible. We do so by (i) building a new wireless hardware platform with appropriate characteristics for making dominance-based MAC protocols efficient, (ii) implementing dominance-based MAC protocols on this platform, (iii) implementing distributed algorithms for aggregate computations (MIN, MAX, Interpolation) using the new implementation of the dominance-based MAC protocol and (iv) performing experiments to prove that such highly scalable aggregate computations in wireless networks are possible.

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The availability of small inexpensive sensor elements enables the employment of large wired or wireless sensor networks for feeding control systems. Unfortunately, the need to transmit a large number of sensor measurements over a network negatively affects the timing parameters of the control loop. This paper presents a solution to this problem by representing sensor measurements with an approximate representation-an interpolation of sensor measurements as a function of space coordinates. A priority-based medium access control (MAC) protocol is used to select the sensor messages with high information content. Thus, the information from a large number of sensor measurements is conveyed within a few messages. This approach greatly reduces the time for obtaining a snapshot of the environment state and therefore supports the real-time requirements of feedback control loops.

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The simulation analysis is important approach to developing and evaluating the systems in terms of development time and cost. This paper demonstrates the application of Time Division Cluster Scheduling (TDCS) tool for the configuration of IEEE 802.15.4/ZigBee beaconenabled cluster-tree WSNs using the simulation analysis, as an illustrative example that confirms the practical applicability of the tool. The simulation study analyses how the number of retransmissions impacts the reliability of data transmission, the energy consumption of the nodes and the end-to-end communication delay, based on the simulation model that was implemented in the Opnet Modeler. The configuration parameters of the network are obtained directly from the TDCS tool. The simulation results show that the number of retransmissions impacts the reliability, the energy consumption and the end-to-end delay, in a way that improving the one may degrade the others.

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This paper proposes an efficient scalable Residue Number System (RNS) architecture supporting moduli sets with an arbitrary number of channels, allowing to achieve larger dynamic range and a higher level of parallelism. The proposed architecture allows the forward and reverse RNS conversion, by reusing the arithmetic channel units. The arithmetic operations supported at the channel level include addition, subtraction, and multiplication with accumulation capability. For the reverse conversion two algorithms are considered, one based on the Chinese Remainder Theorem and the other one on Mixed-Radix-Conversion, leading to implementations optimized for delay and required circuit area. With the proposed architecture a complete and compact RNS platform is achieved. Experimental results suggest gains of 17 % in the delay in the arithmetic operations, with an area reduction of 23 % regarding the RNS state of the art. When compared with a binary system the proposed architecture allows to perform the same computation 20 times faster alongside with only 10 % of the circuit area resources.

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This paper presents a single precision floating point arithmetic unit with support for multiplication, addition, fused multiply-add, reciprocal, square-root and inverse squareroot with high-performance and low resource usage. The design uses a piecewise 2nd order polynomial approximation to implement reciprocal, square-root and inverse square-root. The unit can be configured with any number of operations and is capable to calculate any function with a throughput of one operation per cycle. The floatingpoint multiplier of the unit is also used to implement the polynomial approximation and the fused multiply-add operation. We have compared our implementation with other state-of-the-art proposals, including the Xilinx Core-Gen operators, and conclude that the approach has a high relative performance/area efficiency. © 2014 Technical University of Munich (TUM).

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Dissertação de Mestrado em Engenharia Informática

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Feature selection is a central problem in machine learning and pattern recognition. On large datasets (in terms of dimension and/or number of instances), using search-based or wrapper techniques can be cornputationally prohibitive. Moreover, many filter methods based on relevance/redundancy assessment also take a prohibitively long time on high-dimensional. datasets. In this paper, we propose efficient unsupervised and supervised feature selection/ranking filters for high-dimensional datasets. These methods use low-complexity relevance and redundancy criteria, applicable to supervised, semi-supervised, and unsupervised learning, being able to act as pre-processors for computationally intensive methods to focus their attention on smaller subsets of promising features. The experimental results, with up to 10(5) features, show the time efficiency of our methods, with lower generalization error than state-of-the-art techniques, while being dramatically simpler and faster.

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The aim of the present work is to provide insight into the mechanism of laccase reactions using syringyl-type mediators. We studied the pH dependence and the kinetics of oxidation of syringyl-type phenolics using the low CotA and the high redox potential TvL laccases. Additionally, the efficiency of these compounds as redox mediators for the oxidation of non-phenolic lignin units was tested at different pH values and increasing mediator/non-phenolic ratios. Finally, the intermediates and products of reactions were identified by LC-MS and H-1 NMR. These approaches allow concluding on the (1) mechanism involved in the oxidation of phenolics by bacterial laccases, (2) importance of the chemical nature and properties of phenolic mediators, (3) apparent independence of the enzyme's properties on the yields of non-phenolics conversion, (4) competitive routes involved in the catalytic cycle of the laccase-mediator system with several new C-O coupling type structures being proposed.

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Empowered by virtualisation technology, cloud infrastructures enable the construction of flexi- ble and elastic computing environments, providing an opportunity for energy and resource cost optimisation while enhancing system availability and achieving high performance. A crucial re- quirement for effective consolidation is the ability to efficiently utilise system resources for high- availability computing and energy-efficiency optimisation to reduce operational costs and carbon footprints in the environment. Additionally, failures in highly networked computing systems can negatively impact system performance substantially, prohibiting the system from achieving its initial objectives. In this paper, we propose algorithms to dynamically construct and readjust vir- tual clusters to enable the execution of users’ jobs. Allied with an energy optimising mechanism to detect and mitigate energy inefficiencies, our decision-making algorithms leverage virtuali- sation tools to provide proactive fault-tolerance and energy-efficiency to virtual clusters. We conducted simulations by injecting random synthetic jobs and jobs using the latest version of the Google cloud tracelogs. The results indicate that our strategy improves the work per Joule ratio by approximately 12.9% and the working efficiency by almost 15.9% compared with other state-of-the-art algorithms.

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IEEE International Symposium on Circuits and Systems, pp. 220 – 223, Seattle, EUA

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In search of an efficient but simple, low cost procedure for the serodiagnosis of Toxoplasmosis, especially suited for routine laboratories facing technical and budget limitations as in less developed countries, the diagnostic capability of Hematoxo® , an hemagglutination test for toxoplasmosis, was evaluated in relation to a battery of tests including IgG- and IgM-immunofluorescence tests, hemagglutination and an IgM-capture enzymatic assay. Detecting a little as 5 I.U. of IgG antitoxoplasma antibodies, Hematoxo® showed a straight agreement as to reactivity and non-reactivity for the 443 non-reactive and the 387 reactive serum samples, included in this study. In 23 cases presenting a serological pattern of acute toxoplasmosis and showing IgM antibodies, Hematoxo® could detect IgM antibodies in 18, indicated by negativation or a significant decrease in titers as a result of treating samples with 2-mercapto-ethanol. However, a neat increase in sensitivity for IgM specific antibodies could be achieved by previously removing IgG from the sample, as demonstrated in a series of acute toxoplasmosis sera. A simple procedure was developed for this purpose, by reconstituting a lyophilized suspension of Protein A - rich Staphylococcus with the lowest serum dilution to be tested. Of low cost and easy to perform, Hematoxo® affords not only a practical qualitative procedure for screening reactors and non-reactors, as in prenatal services, but also quantitative assays that permit to titrate antibodies as well as to identify IgM antibodies.

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Proceedings of IEEE, ISCAS 2003, Vol.I, pp. 877-880

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Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

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The need to increase agricultural yield led, among others, to an increase in the consumption of nitrogen based fertilizers. As a consequence, there are excessive concentrations of nitrates, the most abundant of the reactive nitrogen (Nr) species, in several areas of the world. The demographic changes and projected population growth for the next decades, and the economic shifts which are already shaping the near future are powerful drivers for a further intensification in the use of fertilizers, with a predicted increase of the nitrogen loads in soils. Nitrate easily diffuses in the subsurface environments, portraying high mobility in soils. Moreover, the presence of high nitrate loads in water has the potential to cause an array of health dysfunctions, such as methemoglobinemia and several cancers. Permeable Reactive Barriers (PRB) placed strategically relatively to the nitrate source constitute an effective technology to tackle nitrate pollution. Ergo, PRB avoid various adverse impacts resulting from the displacement of reactive nitrogen downstream along water bodies. A four stages literature review was carried out in 34 databases. Initially, a set of pertinent key words were identified to perform the initial databases searches. Then, the synonyms of those initial key words were used to carry out a second set of databases searches. The third stage comprised the identification of other additional relevant terms from the research papers identified in the previous two stages. Again, databases searches were performed with this third set of key words. The final step consisted of the identification of relevant papers from the bibliography of the relevant papers identified in the previous three stages of the literature review process. The set of papers identified as relevant for in-depth analysis were assessed considering a set of relevant characterization variables.

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Task scheduling is one of the key mechanisms to ensure timeliness in embedded real-time systems. Such systems have often the need to execute not only application tasks but also some urgent routines (e.g. error-detection actions, consistency checkers, interrupt handlers) with minimum latency. Although fixed-priority schedulers such as Rate-Monotonic (RM) are in line with this need, they usually make a low processor utilization available to the system. Moreover, this availability usually decreases with the number of considered tasks. If dynamic-priority schedulers such as Earliest Deadline First (EDF) are applied instead, high system utilization can be guaranteed but the minimum latency for executing urgent routines may not be ensured. In this paper we describe a scheduling model according to which urgent routines are executed at the highest priority level and all other system tasks are scheduled by EDF. We show that the guaranteed processor utilization for the assumed scheduling model is at least as high as the one provided by RM for two tasks, namely 2(2√−1). Seven polynomial time tests for checking the system timeliness are derived and proved correct. The proposed tests are compared against each other and to an exact but exponential running time test.