Phenolic contents of lettuce, strawberry, raspberry, and blueberry crops cultivated under plastic films varying in ultraviolet transparency

The levels of health-related phytochemicals were determined in lettuce leaf and in strawberry, raspberry and blueberry fruits grown in near-commercial conditions under plastic films of three different UV transparencies. In the red lettuce Lollo Rosso, total phenolics, anthocyanin, luteolin and quercetin levels were all raised by changing from a UV blocking film to a film of low UV transparency, and to a film of high UV transparency. The related green lettuce, Lollo Biondo, cultivated under the same conditions, showed virtually no phytochemical responses to the same variation in UV levels. Overall, the phenolic levels of strawberries, raspberries, and blueberries were unresponsive to the UV transparency of the plastic film under which the crops were grown. The significance of these findings is discussed in relation to the nutritional quality of soft fruit and salad crops which are increasingly being grown commercially under plastic tunnels.

Changes in the flavonoid and phenolic acid contents and antioxidant activity of red leaf lettuce (Lollo Rosso) due to cultivation under plastic films varying in ultraviolet transparency

Red leaf lettuce (Lollo Rosso) was grown under three types of plastic films that varied in transparency to UV radiation (designated as UV block, UV low, and UV window). Flavonoid composition was determined by high-performance liquid chromatography (HPLC), total phenolics by the Folin-Ciocalteu assay, and antioxiclant capacity by the oxygen radical absorbance capacity (ORAC) assay. Exposure to increased levels of UV radiation during cultivation caused the leaves to redden and increased concentrations of total phenols and the main flavonoids, quercetin and cyanidin glycosides, as well as luteolin conjugates and phenolic acids. The total phenol content increased from 1.6 mg of gallic acid equivalents (GAE)/g of fresh weight (FW) for lettuce grown under UV block film to 2.9 and 3.5 mg of GAE/g of FW for lettuce grown under the UV low and UV window films. The antioxiclant activity was also higher in lettuce exposed to higher levels of UV radiation with ORAC values of 25.4 and 55.1 mu mol of Trolox equivalents/g of FW for lettuce grown under the UV block and UV window films, respectively. The content of phenolic acids, quantified as caffeic acid, was also different, ranging from 6.2 to 11.1 mu mol/g of FW for lettuce cultivated under the lowest and highest UV exposure plastic films, respectively. Higher concentrations of the flavonoid glycosides were observed with increased exposure to UV radiation, as demonstrated by the concentrations of aglycones after hydrolysis, which were cyanidin (ranging from 165 to 793 mu g/g), quercetin (ranging from 196 to 880,mu g/g), and luteolin (ranging from 19 to 152 mu g/g). The results demonstrate the potential of the use of UV-transparent plastic as a means of increasing beneficial flavonoid content of red leaf lettuce when the crop is grown in polytunnels.

Changes in the flavonoid and phenolic acid contents and antioxidant activity of red leaf lettuce (Lollo Rosso) due to cultivation under plastic films varying in ultraviolet transparency

Red leaf lettuce (Lollo Rosso) was grown under three types of plastic films that varied in transparency to UV radiation (designated as UV block, UV low, and UV window). Flavonoid composition was determined by high-performance liquid chromatography (HPLC), total phenolics by the Folin-Ciocalteu assay, and antioxiclant capacity by the oxygen radical absorbance capacity (ORAC) assay. Exposure to increased levels of UV radiation during cultivation caused the leaves to redden and increased concentrations of total phenols and the main flavonoids, quercetin and cyanidin glycosides, as well as luteolin conjugates and phenolic acids. The total phenol content increased from 1.6 mg of gallic acid equivalents (GAE)/g of fresh weight (FW) for lettuce grown under UV block film to 2.9 and 3.5 mg of GAE/g of FW for lettuce grown under the UV low and UV window films. The antioxiclant activity was also higher in lettuce exposed to higher levels of UV radiation with ORAC values of 25.4 and 55.1 mu mol of Trolox equivalents/g of FW for lettuce grown under the UV block and UV window films, respectively. The content of phenolic acids, quantified as caffeic acid, was also different, ranging from 6.2 to 11.1 mu mol/g of FW for lettuce cultivated under the lowest and highest UV exposure plastic films, respectively. Higher concentrations of the flavonoid glycosides were observed with increased exposure to UV radiation, as demonstrated by the concentrations of aglycones after hydrolysis, which were cyanidin (ranging from 165 to 793 mu g/g), quercetin (ranging from 196 to 880,mu g/g), and luteolin (ranging from 19 to 152 mu g/g). The results demonstrate the potential of the use of UV-transparent plastic as a means of increasing beneficial flavonoid content of red leaf lettuce when the crop is grown in polytunnels.

Perspectives on community representation within the Extractive Industries Transparency Initiative: experiences from south-east Madagascar

This article critically examines the nature and quality of governance in community representation and civil society engagement in the context of trans-national large-scale mining, drawing on experiences in the Anosy Region of south-east Madagascar. An exploration of functional relationships between government, mining business and civil society stakeholders reveals an equivocal legitimacy of certain civil society representatives, created by state manipulation, which contributes to community disempowerment. The appointment of local government officials, rather than election, creates a hierarchy of upward dependencies and a culture where the majority of officials express similar views and political alliances. As a consequence, community resistance is suppressed. Voluntary mechanisms such as Corporate Social Responsibility (CSR) and the Extractive Industries Transparency Initiative (EITI) advocate community stakeholder engagement in decision making processes as a measure to achieve public accountability. In many developing countries, where there is a lack of transparency and high levels of corruption, the value of this engagement, however, is debatable. Findings from this study indicate that the power relationships which exist between stakeholders in the highly lucrative mining industry override efforts to achieve "good governance" through voluntary community engagement. The continuing challenge lies in identifying where the responsibility sits in order to address this power struggle to achieve fair representation.

Are informed citizens more trusting? Transparency of performance data and trust towards a British police force

In Britain, substantial cuts in police budgets alongside controversial handling of incidents such as politically sensitive enquiries, public disorder and relations with the media have recently triggered much debate about public knowledge and trust in the police. To date, however, little academic research has investigated how knowledge of police performance impacts citizens’ trust. We address this long-standing lacuna by exploring citizens’ trust before and after exposure to real performance data in the context of a British police force. The results reveal that being informed of performance data affects citizens’ trust significantly. Furthermore, direction and degree of change in trust are related to variations across the different elements of the reported performance criteria. Interestingly, the volatility of citizens’ trust is related to initial performance perceptions (such that citizens with low initial perceptions of police performance react more significantly to evidence of both good and bad performance than citizens with high initial perceptions), and citizens’ intentions to support the police do not always correlate with their cognitive and affective trust towards the police. In discussing our findings, we explore the implications of how being transparent with performance data can both hinder and be helpful in developing citizens’ trust towards a public organisation such as the police. From our study, we pose a number of ethical challenges that practitioners face when deciding what data to highlight, to whom, and for what purpose.

Quantum control of electromagnetically induced transparency dispersion via atomic tunneling in a double-well Bose-Einstein condensate

Electromagnetically induced transparency (EIT) is an important tool for controlling light propagation and nonlinear wave mixing in atomic gases with potential applications ranging from quantum computing to table top tests of general relativity. Here we consider EIT in an atomic Bose-Einstein condensate (BEC) trapped in a double-well potential. A weak probe laser propagates through one of the wells and interacts with atoms in a three-level Lambda configuration. The well through which the probe propagates is dressed by a strong control laser with Rabi frequency Omega(mu), as in standard EIT systems. Tunneling between the wells at the frequency g provides a coherent coupling between identical electronic states in the two wells, which leads to the formation of interwell dressed states. The macroscopic interwell coherence of the BEC wave function results in the formation of two ultranarrow absorption resonances for the probe field that are inside of the ordinary EIT transparency window. We show that these new resonances can be interpreted in terms of the interwell dressed states and the formation of a type of dark state involving the control laser and the interwell tunneling. To either side of these ultranarrow resonances there is normal dispersion with very large slope controlled by g. We discuss prospects for observing these ultranarrow resonances and the corresponding regions of high dispersion experimentally.

Melting Alpine Glaciers Enrich High-Elevation Lakes with Reactive Nitrogen

Alpine glaciers have receded substantially over the last century in many regions of the world. Resulting changes in glacial runoff not only affect the hydrological cycle, but can also alter the physical (i.e., turbidity from glacial flour) and biogeochemical properties of downstream ecosystems. Here we compare nutrient concentrations, transparency gradients, algal biomass, and fossil diatom species richness in two sets of high-elevation lakes: those fed by snowpack melt alone (SF lakes) and those fed by both glacial and snowpack meltwaters (GSF lakes). We found that nitrate (NO3-) concentrations in the GSF lakes were 1-2 orders of magnitude higher than in SF lakes. Although nitrogen (N) limitation is common in alpine lakes, algal biomass was lower in highly N-enriched GSF lakes than in the N-poor SF lakes. Contrary to expectations, GSF lakes were more transparent than SF lakes to ultraviolet and equally transparent to photosynthetically active radiation.Sediment diatom assemblages had lower taxonomic richness in the GSF lakes, a feature that has persisted over the last century. Our results demonstrate that the presence of glaciers on alpine watersheds more strongly influences NO3- concentrations in high-elevation lake ecosystems than any other geomorphic or biogeographic characteristic.

Creating a public tool to assess and promote transparency in global land deals: the experience of the Land Matrix

The Beta version of the Land Matrix (Land Matrix 2012) was launched in April 2012 as a tool to promote public participation in building a constantly evolving database on large-scale land deals, and making the data visible and understandable. The aim of the Land Matrix partnership is to promote transparency and open data in decisionmaking over land and investment, as a step towards greater accountability. Since its launch, the Land Matrix has attracted a high degree of attention, and stirred some controversy. It provides valuable lessons on the challenges and benefits of promoting open data on practices that are often shrouded in secrecy. This paper critically examines the ongoing efforts by the Land Matrix partnership to build a public tool to promote greater transparency in decision-making over land and investment at a global level. It intends to provoke discussion of the extent to which such a tool can ultimately promote greater transparency and be a step towards greater accountability and improved decision-making. It will present the Land Matrix and its value addition, before detailing the challenges it encountered related to the measurement of the largescale land acquisition phenomenon. It will then specify how it intends to address these issues in order to establish a dynamic and participatory tool for open development.

Highly conductive p++-AlGaAs/n ++-GaInP tunnel junctions for ultra-high concentrator solar cells

Tunnel junctions are key for developing multijunction solar cells (MJSC) for ultra-high concentration applications. We have developed a highly conductive, high bandgap p  + + -AlGaAs/n  + + -GaInP tunnel junction with a peak tunneling current density for as-grown and thermal annealed devices of 996 A/cm 2 and 235 A/cm 2, respectively. The J–V characteristics of the tunnel junction after thermal annealing, together with its behavior at MJSCs typical operation temperatures, indicate that this tunnel junction is a suitable candidate for ultra-high concentrator MJSC designs. The benefits of the optical transparency are also assessed for a lattice-matched GaInP/GaInAs/Ge triple junction solar cell, yielding a current density increase in the middle cell of 0.506 mA/cm 2 with respect to previous designs.

Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems

Esta tesis doctoral se enmarca dentro del campo de los sistemas embebidos reconfigurables, redes de sensores inalámbricas para aplicaciones de altas prestaciones, y computación distribuida. El documento se centra en el estudio de alternativas de procesamiento para sistemas embebidos autónomos distribuidos de altas prestaciones (por sus siglas en inglés, High-Performance Autonomous Distributed Systems (HPADS)), así como su evolución hacia el procesamiento de alta resolución. El estudio se ha llevado a cabo tanto a nivel de plataforma como a nivel de las arquitecturas de procesamiento dentro de la plataforma con el objetivo de optimizar aspectos tan relevantes como la eficiencia energética, la capacidad de cómputo y la tolerancia a fallos del sistema. Los HPADS son sistemas realimentados, normalmente formados por elementos distribuidos conectados o no en red, con cierta capacidad de adaptación, y con inteligencia suficiente para llevar a cabo labores de prognosis y/o autoevaluación. Esta clase de sistemas suele formar parte de sistemas más complejos llamados sistemas ciber-físicos (por sus siglas en inglés, Cyber-Physical Systems (CPSs)). Los CPSs cubren un espectro enorme de aplicaciones, yendo desde aplicaciones médicas, fabricación, o aplicaciones aeroespaciales, entre otras muchas. Para el diseño de este tipo de sistemas, aspectos tales como la confiabilidad, la definición de modelos de computación, o el uso de metodologías y/o herramientas que faciliten el incremento de la escalabilidad y de la gestión de la complejidad, son fundamentales. La primera parte de esta tesis doctoral se centra en el estudio de aquellas plataformas existentes en el estado del arte que por sus características pueden ser aplicables en el campo de los CPSs, así como en la propuesta de un nuevo diseño de plataforma de altas prestaciones que se ajuste mejor a los nuevos y más exigentes requisitos de las nuevas aplicaciones. Esta primera parte incluye descripción, implementación y validación de la plataforma propuesta, así como conclusiones sobre su usabilidad y sus limitaciones. Los principales objetivos para el diseño de la plataforma propuesta se enumeran a continuación: • Estudiar la viabilidad del uso de una FPGA basada en RAM como principal procesador de la plataforma en cuanto a consumo energético y capacidad de cómputo. • Propuesta de técnicas de gestión del consumo de energía en cada etapa del perfil de trabajo de la plataforma. •Propuestas para la inclusión de reconfiguración dinámica y parcial de la FPGA (por sus siglas en inglés, Dynamic Partial Reconfiguration (DPR)) de forma que sea posible cambiar ciertas partes del sistema en tiempo de ejecución y sin necesidad de interrumpir al resto de las partes. Evaluar su aplicabilidad en el caso de HPADS. Las nuevas aplicaciones y nuevos escenarios a los que se enfrentan los CPSs, imponen nuevos requisitos en cuanto al ancho de banda necesario para el procesamiento de los datos, así como en la adquisición y comunicación de los mismos, además de un claro incremento en la complejidad de los algoritmos empleados. Para poder cumplir con estos nuevos requisitos, las plataformas están migrando desde sistemas tradicionales uni-procesador de 8 bits, a sistemas híbridos hardware-software que incluyen varios procesadores, o varios procesadores y lógica programable. Entre estas nuevas arquitecturas, las FPGAs y los sistemas en chip (por sus siglas en inglés, System on Chip (SoC)) que incluyen procesadores embebidos y lógica programable, proporcionan soluciones con muy buenos resultados en cuanto a consumo energético, precio, capacidad de cómputo y flexibilidad. Estos buenos resultados son aún mejores cuando las aplicaciones tienen altos requisitos de cómputo y cuando las condiciones de trabajo son muy susceptibles de cambiar en tiempo real. La plataforma propuesta en esta tesis doctoral se ha denominado HiReCookie. La arquitectura incluye una FPGA basada en RAM como único procesador, así como un diseño compatible con la plataforma para redes de sensores inalámbricas desarrollada en el Centro de Electrónica Industrial de la Universidad Politécnica de Madrid (CEI-UPM) conocida como Cookies. Esta FPGA, modelo Spartan-6 LX150, era, en el momento de inicio de este trabajo, la mejor opción en cuanto a consumo y cantidad de recursos integrados, cuando además, permite el uso de reconfiguración dinámica y parcial. Es importante resaltar que aunque los valores de consumo son los mínimos para esta familia de componentes, la potencia instantánea consumida sigue siendo muy alta para aquellos sistemas que han de trabajar distribuidos, de forma autónoma, y en la mayoría de los casos alimentados por baterías. Por esta razón, es necesario incluir en el diseño estrategias de ahorro energético para incrementar la usabilidad y el tiempo de vida de la plataforma. La primera estrategia implementada consiste en dividir la plataforma en distintas islas de alimentación de forma que sólo aquellos elementos que sean estrictamente necesarios permanecerán alimentados, cuando el resto puede estar completamente apagado. De esta forma es posible combinar distintos modos de operación y así optimizar enormemente el consumo de energía. El hecho de apagar la FPGA para ahora energía durante los periodos de inactividad, supone la pérdida de la configuración, puesto que la memoria de configuración es una memoria volátil. Para reducir el impacto en el consumo y en el tiempo que supone la reconfiguración total de la plataforma una vez encendida, en este trabajo, se incluye una técnica para la compresión del archivo de configuración de la FPGA, de forma que se consiga una reducción del tiempo de configuración y por ende de la energía consumida. Aunque varios de los requisitos de diseño pueden satisfacerse con el diseño de la plataforma HiReCookie, es necesario seguir optimizando diversos parámetros tales como el consumo energético, la tolerancia a fallos y la capacidad de procesamiento. Esto sólo es posible explotando todas las posibilidades ofrecidas por la arquitectura de procesamiento en la FPGA. Por lo tanto, la segunda parte de esta tesis doctoral está centrada en el diseño de una arquitectura reconfigurable denominada ARTICo3 (Arquitectura Reconfigurable para el Tratamiento Inteligente de Cómputo, Confiabilidad y Consumo de energía) para la mejora de estos parámetros por medio de un uso dinámico de recursos. ARTICo3 es una arquitectura de procesamiento para FPGAs basadas en RAM, con comunicación tipo bus, preparada para dar soporte para la gestión dinámica de los recursos internos de la FPGA en tiempo de ejecución gracias a la inclusión de reconfiguración dinámica y parcial. Gracias a esta capacidad de reconfiguración parcial, es posible adaptar los niveles de capacidad de procesamiento, energía consumida o tolerancia a fallos para responder a las demandas de la aplicación, entorno, o métricas internas del dispositivo mediante la adaptación del número de recursos asignados para cada tarea. Durante esta segunda parte de la tesis se detallan el diseño de la arquitectura, su implementación en la plataforma HiReCookie, así como en otra familia de FPGAs, y su validación por medio de diferentes pruebas y demostraciones. Los principales objetivos que se plantean la arquitectura son los siguientes: • Proponer una metodología basada en un enfoque multi-hilo, como las propuestas por CUDA (por sus siglas en inglés, Compute Unified Device Architecture) u Open CL, en la cual distintos kernels, o unidades de ejecución, se ejecuten en un numero variable de aceleradores hardware sin necesidad de cambios en el código de aplicación. • Proponer un diseño y proporcionar una arquitectura en la que las condiciones de trabajo cambien de forma dinámica dependiendo bien de parámetros externos o bien de parámetros que indiquen el estado de la plataforma. Estos cambios en el punto de trabajo de la arquitectura serán posibles gracias a la reconfiguración dinámica y parcial de aceleradores hardware en tiempo real. • Explotar las posibilidades de procesamiento concurrente, incluso en una arquitectura basada en bus, por medio de la optimización de las transacciones en ráfaga de datos hacia los aceleradores. •Aprovechar las ventajas ofrecidas por la aceleración lograda por módulos puramente hardware para conseguir una mejor eficiencia energética. • Ser capaces de cambiar los niveles de redundancia de hardware de forma dinámica según las necesidades del sistema en tiempo real y sin cambios para el código de aplicación. • Proponer una capa de abstracción entre el código de aplicación y el uso dinámico de los recursos de la FPGA. El diseño en FPGAs permite la utilización de módulos hardware específicamente creados para una aplicación concreta. De esta forma es posible obtener rendimientos mucho mayores que en el caso de las arquitecturas de propósito general. Además, algunas FPGAs permiten la reconfiguración dinámica y parcial de ciertas partes de su lógica en tiempo de ejecución, lo cual dota al diseño de una gran flexibilidad. Los fabricantes de FPGAs ofrecen arquitecturas predefinidas con la posibilidad de añadir bloques prediseñados y poder formar sistemas en chip de una forma más o menos directa. Sin embargo, la forma en la que estos módulos hardware están organizados dentro de la arquitectura interna ya sea estática o dinámicamente, o la forma en la que la información se intercambia entre ellos, influye enormemente en la capacidad de cómputo y eficiencia energética del sistema. De la misma forma, la capacidad de cargar módulos hardware bajo demanda, permite añadir bloques redundantes que permitan aumentar el nivel de tolerancia a fallos de los sistemas. Sin embargo, la complejidad ligada al diseño de bloques hardware dedicados no debe ser subestimada. Es necesario tener en cuenta que el diseño de un bloque hardware no es sólo su propio diseño, sino también el diseño de sus interfaces, y en algunos casos de los drivers software para su manejo. Además, al añadir más bloques, el espacio de diseño se hace más complejo, y su programación más difícil. Aunque la mayoría de los fabricantes ofrecen interfaces predefinidas, IPs (por sus siglas en inglés, Intelectual Property) comerciales y plantillas para ayudar al diseño de los sistemas, para ser capaces de explotar las posibilidades reales del sistema, es necesario construir arquitecturas sobre las ya establecidas para facilitar el uso del paralelismo, la redundancia, y proporcionar un entorno que soporte la gestión dinámica de los recursos. Para proporcionar este tipo de soporte, ARTICo3 trabaja con un espacio de soluciones formado por tres ejes fundamentales: computación, consumo energético y confiabilidad. De esta forma, cada punto de trabajo se obtiene como una solución de compromiso entre estos tres parámetros. Mediante el uso de la reconfiguración dinámica y parcial y una mejora en la transmisión de los datos entre la memoria principal y los aceleradores, es posible dedicar un número variable de recursos en el tiempo para cada tarea, lo que hace que los recursos internos de la FPGA sean virtualmente ilimitados. Este variación en el tiempo del número de recursos por tarea se puede usar bien para incrementar el nivel de paralelismo, y por ende de aceleración, o bien para aumentar la redundancia, y por lo tanto el nivel de tolerancia a fallos. Al mismo tiempo, usar un numero óptimo de recursos para una tarea mejora el consumo energético ya que bien es posible disminuir la potencia instantánea consumida, o bien el tiempo de procesamiento. Con el objetivo de mantener los niveles de complejidad dentro de unos límites lógicos, es importante que los cambios realizados en el hardware sean totalmente transparentes para el código de aplicación. A este respecto, se incluyen distintos niveles de transparencia: • Transparencia a la escalabilidad: los recursos usados por una misma tarea pueden ser modificados sin que el código de aplicación sufra ningún cambio. • Transparencia al rendimiento: el sistema aumentara su rendimiento cuando la carga de trabajo aumente, sin cambios en el código de aplicación. • Transparencia a la replicación: es posible usar múltiples instancias de un mismo módulo bien para añadir redundancia o bien para incrementar la capacidad de procesamiento. Todo ello sin que el código de aplicación cambie. • Transparencia a la posición: la posición física de los módulos hardware es arbitraria para su direccionamiento desde el código de aplicación. • Transparencia a los fallos: si existe un fallo en un módulo hardware, gracias a la redundancia, el código de aplicación tomará directamente el resultado correcto. • Transparencia a la concurrencia: el hecho de que una tarea sea realizada por más o menos bloques es transparente para el código que la invoca. Por lo tanto, esta tesis doctoral contribuye en dos líneas diferentes. En primer lugar, con el diseño de la plataforma HiReCookie y en segundo lugar con el diseño de la arquitectura ARTICo3. Las principales contribuciones de esta tesis se resumen a continuación. • Arquitectura de la HiReCookie incluyendo: o Compatibilidad con la plataforma Cookies para incrementar las capacidades de esta. o División de la arquitectura en distintas islas de alimentación. o Implementación de los diversos modos de bajo consumo y políticas de despertado del nodo. o Creación de un archivo de configuración de la FPGA comprimido para reducir el tiempo y el consumo de la configuración inicial. • Diseño de la arquitectura reconfigurable para FPGAs basadas en RAM ARTICo3: o Modelo de computación y modos de ejecución inspirados en el modelo de CUDA pero basados en hardware reconfigurable con un número variable de bloques de hilos por cada unidad de ejecución. o Estructura para optimizar las transacciones de datos en ráfaga proporcionando datos en cascada o en paralelo a los distinto módulos incluyendo un proceso de votado por mayoría y operaciones de reducción. o Capa de abstracción entre el procesador principal que incluye el código de aplicación y los recursos asignados para las diferentes tareas. o Arquitectura de los módulos hardware reconfigurables para mantener la escalabilidad añadiendo una la interfaz para las nuevas funcionalidades con un simple acceso a una memoria RAM interna. o Caracterización online de las tareas para proporcionar información a un módulo de gestión de recursos para mejorar la operación en términos de energía y procesamiento cuando además se opera entre distintos nieles de tolerancia a fallos. El documento está dividido en dos partes principales formando un total de cinco capítulos. En primer lugar, después de motivar la necesidad de nuevas plataformas para cubrir las nuevas aplicaciones, se detalla el diseño de la plataforma HiReCookie, sus partes, las posibilidades para bajar el consumo energético y se muestran casos de uso de la plataforma así como pruebas de validación del diseño. La segunda parte del documento describe la arquitectura reconfigurable, su implementación en varias FPGAs, y pruebas de validación en términos de capacidad de procesamiento y consumo energético, incluyendo cómo estos aspectos se ven afectados por el nivel de tolerancia a fallos elegido. Los capítulos a lo largo del documento son los siguientes: El capítulo 1 analiza los principales objetivos, motivación y aspectos teóricos necesarios para seguir el resto del documento. El capítulo 2 está centrado en el diseño de la plataforma HiReCookie y sus posibilidades para disminuir el consumo de energía. El capítulo 3 describe la arquitectura reconfigurable ARTICo3. El capítulo 4 se centra en las pruebas de validación de la arquitectura usando la plataforma HiReCookie para la mayoría de los tests. Un ejemplo de aplicación es mostrado para analizar el funcionamiento de la arquitectura. El capítulo 5 concluye esta tesis doctoral comentando las conclusiones obtenidas, las contribuciones originales del trabajo y resultados y líneas futuras. ABSTRACT This PhD Thesis is framed within the field of dynamically reconfigurable embedded systems, advanced sensor networks and distributed computing. The document is centred on the study of processing solutions for high-performance autonomous distributed systems (HPADS) as well as their evolution towards High performance Computing (HPC) systems. The approach of the study is focused on both platform and processor levels to optimise critical aspects such as computing performance, energy efficiency and fault tolerance. HPADS are considered feedback systems, normally networked and/or distributed, with real-time adaptive and predictive functionality. These systems, as part of more complex systems known as Cyber-Physical Systems (CPSs), can be applied in a wide range of fields such as military, health care, manufacturing, aerospace, etc. For the design of HPADS, high levels of dependability, the definition of suitable models of computation, and the use of methodologies and tools to support scalability and complexity management, are required. The first part of the document studies the different possibilities at platform design level in the state of the art, together with description, development and validation tests of the platform proposed in this work to cope with the previously mentioned requirements. The main objectives targeted by this platform design are the following: • Study the feasibility of using SRAM-based FPGAs as the main processor of the platform in terms of energy consumption and performance for high demanding applications. • Analyse and propose energy management techniques to reduce energy consumption in every stage of the working profile of the platform. • Provide a solution with dynamic partial and wireless remote HW reconfiguration (DPR) to be able to change certain parts of the FPGA design at run time and on demand without interrupting the rest of the system. • Demonstrate the applicability of the platform in different test-bench applications. In order to select the best approach for the platform design in terms of processing alternatives, a study of the evolution of the state-of-the-art platforms is required to analyse how different architectures cope with new more demanding applications and scenarios: security, mixed-critical systems for aerospace, multimedia applications, or military environments, among others. In all these scenarios, important changes in the required processing bandwidth or the complexity of the algorithms used are provoking the migration of the platforms from single microprocessor architectures to multiprocessing and heterogeneous solutions with more instant power consumption but higher energy efficiency. Within these solutions, FPGAs and Systems on Chip including FPGA fabric and dedicated hard processors, offer a good trade of among flexibility, processing performance, energy consumption and price, when they are used in demanding applications where working conditions are very likely to vary over time and high complex algorithms are required. The platform architecture proposed in this PhD Thesis is called HiReCookie. It includes an SRAM-based FPGA as the main and only processing unit. The FPGA selected, the Xilinx Spartan-6 LX150, was at the beginning of this work the best choice in terms of amount of resources and power. Although, the power levels are the lowest of these kind of devices, they can be still very high for distributed systems that normally work powered by batteries. For that reason, it is necessary to include different energy saving possibilities to increase the usability of the platform. In order to reduce energy consumption, the platform architecture is divided into different power islands so that only those parts of the systems that are strictly needed are powered on, while the rest of the islands can be completely switched off. This allows a combination of different low power modes to decrease energy. In addition, one of the most important handicaps of SRAM-based FPGAs is that they are not alive at power up. Therefore, recovering the system from a switch-off state requires to reload the FPGA configuration from a non-volatile memory device. For that reason, this PhD Thesis also proposes a methodology to compress the FPGA configuration file in order to reduce time and energy during the initial configuration process. Although some of the requirements for the design of HPADS are already covered by the design of the HiReCookie platform, it is necessary to continue improving energy efficiency, computing performance and fault tolerance. This is only possible by exploiting all the opportunities provided by the processing architectures configured inside the FPGA. Therefore, the second part of the thesis details the design of the so called ARTICo3 FPGA architecture to enhance the already intrinsic capabilities of the FPGA. ARTICo3 is a DPR-capable bus-based virtual architecture for multiple HW acceleration in SRAM-based FPGAs. The architecture provides support for dynamic resource management in real time. In this way, by using DPR, it will be possible to change the levels of computing performance, energy consumption and fault tolerance on demand by increasing or decreasing the amount of resources used by the different tasks. Apart from the detailed design of the architecture and its implementation in different FPGA devices, different validation tests and comparisons are also shown. The main objectives targeted by this FPGA architecture are listed as follows: • Provide a method based on a multithread approach such as those offered by CUDA (Compute Unified Device Architecture) or OpenCL kernel executions, where kernels are executed in a variable number of HW accelerators without requiring application code changes. • Provide an architecture to dynamically adapt working points according to either self-measured or external parameters in terms of energy consumption, fault tolerance and computing performance. Taking advantage of DPR capabilities, the architecture must provide support for a dynamic use of resources in real time. • Exploit concurrent processing capabilities in a standard bus-based system by optimizing data transactions to and from HW accelerators. • Measure the advantage of HW acceleration as a technique to boost performance to improve processing times and save energy by reducing active times for distributed embedded systems. • Dynamically change the levels of HW redundancy to adapt fault tolerance in real time. • Provide HW abstraction from SW application design. FPGAs give the possibility of designing specific HW blocks for every required task to optimise performance while some of them include the possibility of including DPR. Apart from the possibilities provided by manufacturers, the way these HW modules are organised, addressed and multiplexed in area and time can improve computing performance and energy consumption. At the same time, fault tolerance and security techniques can also be dynamically included using DPR. However, the inherent complexity of designing new HW modules for every application is not negligible. It does not only consist of the HW description, but also the design of drivers and interfaces with the rest of the system, while the design space is widened and more complex to define and program. Even though the tools provided by the majority of manufacturers already include predefined bus interfaces, commercial IPs, and templates to ease application prototyping, it is necessary to improve these capabilities. By adding new architectures on top of them, it is possible to take advantage of parallelization and HW redundancy while providing a framework to ease the use of dynamic resource management. ARTICo3 works within a solution space where working points change at run time in a 3D space defined by three different axes: Computation, Consumption, and Fault Tolerance. Therefore, every working point is found as a trade-off solution among these three axes. By means of DPR, different accelerators can be multiplexed so that the amount of available resources for any application is virtually unlimited. Taking advantage of DPR capabilities and a novel way of transmitting data to the reconfigurable HW accelerators, it is possible to dedicate a dynamically-changing number of resources for a given task in order to either boost computing speed or adding HW redundancy and a voting process to increase fault-tolerance levels. At the same time, using an optimised amount of resources for a given task reduces energy consumption by reducing instant power or computing time. In order to keep level complexity under certain limits, it is important that HW changes are transparent for the application code. Therefore, different levels of transparency are targeted by the system: • Scalability transparency: a task must be able to expand its resources without changing the system structure or application algorithms. • Performance transparency: the system must reconfigure itself as load changes. • Replication transparency: multiple instances of the same task are loaded to increase reliability and performance. • Location transparency: resources are accessed with no knowledge of their location by the application code. • Failure transparency: task must be completed despite a failure in some components. • Concurrency transparency: different tasks will work in a concurrent way transparent to the application code. Therefore, as it can be seen, the Thesis is contributing in two different ways. First with the design of the HiReCookie platform and, second with the design of the ARTICo3 architecture. The main contributions of this PhD Thesis are then listed below: • Architecture of the HiReCookie platform including: o Compatibility of the processing layer for high performance applications with the Cookies Wireless Sensor Network platform for fast prototyping and implementation. o A division of the architecture in power islands. o All the different low-power modes. o The creation of the partial-initial bitstream together with the wake-up policies of the node. • The design of the reconfigurable architecture for SRAM FPGAs: ARTICo3: o A model of computation and execution modes inspired in CUDA but based on reconfigurable HW with a dynamic number of thread blocks per kernel. o A structure to optimise burst data transactions providing coalesced or parallel data to HW accelerators, parallel voting process and reduction operation. o The abstraction provided to the host processor with respect to the operation of the kernels in terms of the number of replicas, modes of operation, location in the reconfigurable area and addressing. o The architecture of the modules representing the thread blocks to make the system scalable by adding functional units only adding an access to a BRAM port. o The online characterization of the kernels to provide information to a scheduler or resource manager in terms of energy consumption and processing time when changing among different fault-tolerance levels, as well as if a kernel is expected to work in the memory-bounded or computing-bounded areas. The document of the Thesis is divided into two main parts with a total of five chapters. First, after motivating the need for new platforms to cover new more demanding applications, the design of the HiReCookie platform, its parts and several partial tests are detailed. The design of the platform alone does not cover all the needs of these applications. Therefore, the second part describes the architecture inside the FPGA, called ARTICo3, proposed in this PhD Thesis. The architecture and its implementation are tested in terms of energy consumption and computing performance showing different possibilities to improve fault tolerance and how this impact in energy and time of processing. Chapter 1 shows the main goals of this PhD Thesis and the technology background required to follow the rest of the document. Chapter 2 shows all the details about the design of the FPGA-based platform HiReCookie. Chapter 3 describes the ARTICo3 architecture. Chapter 4 is focused on the validation tests of the ARTICo3 architecture. An application for proof of concept is explained where typical kernels related to image processing and encryption algorithms are used. Further experimental analyses are performed using these kernels. Chapter 5 concludes the document analysing conclusions, comments about the contributions of the work, and some possible future lines for the work.

Indium-cadmium-oxide films having exceptional electrical conductivity and optical transparency: Clues for optimizing transparent conductors

Materials with high electrical conductivity and optical transparency are needed for future flat panel display, solar energy, and other opto-electronic technologies. InxCd1-xO films having a simple cubic microstructure have been grown on amorphous glass substrates by a straightforward chemical vapor deposition process. The x = 0.05 film conductivity of 17,000 S/cm, carrier mobility of 70 cm2/Vs, and visible region optical transparency window considerably exceed the corresponding parameters for commercial indium-tin oxide. Ab initio electronic structure calculations reveal small conduction electron effective masses, a dramatic shift of the CdO band gap with doping, and a conduction band hybridization gap caused by extensive Cd 5s + In 5s mixing.

Supervisory transparency in the European banking union. Bruegel Policy Contribution 2014/01, 3 January 2004

Bank supervisors should provide publicly accessible, timely and consistent data on the banks under their jurisdiction. Such transparency increases democratic accountability and leads to greater market efficiency. There is greater supervisory transparency in the United States compared to the member states of the European Union. The US supervisors publish data quarterly and update fairly detailed information on bank balance sheets within a week. By contrast, based on an attempt to locate similar data in every EU country, in only 11 member states is this data at least partially available from supervisors, and in no member state is the level of transparency as high as in the US. Current and planned European Union requirements on bank transparency are either insufficient or could be easily sidestepped by supervisors. A banking union in Europe needs to include requirements for greater supervisory transparency.

Financial regulatory transparency: new data and implications for EU policy. Bruegel Policy Brief 2015/20, December 2015

International financial institutions have promoted financial regulatory transparency, or the publication by supervisors of financial industry data. Financial regulatory transparency enhances market stability and increases democratic legitimacy. • We introduce a new index of financial regulatory data transparency: the FRT Index. It measures how countries report to international financial institutions basic macroprudential data about their financial systems.The Index covers 68 high-income and emerging-market economies over 22 years (1990-2011). • We find a number of striking trends over this period. European Union members are generally more opaque than other high-income countries.This finding is especially relevant given efforts to create an EU capital markets union. • Globally, financial regulatory data transparency has increased. However, there is considerable variation. Some countries have become significantlymore transparent, while others have become much more opaque. Reporting tends to decline during financial crises. • We propose that the EU institutions take on a greater role in coordinating and possibly enforcing reporting of bank and non-bank institution data. Similar to the United States, a reporting requirement should be part of any EU general deposit insurance scheme.

Simultaneous spatial and spectral transparency in ultralong fiber lasers

We demonstrate that ultralong Raman lasers can be used to generate a transmission medium with simultaneous transparency over the spatial and the spectral domains. Numerical calculations show this cross-domain transparency to be preserved when the medium is used for transmitting high-intensity signals, which makes ultralong lasers an ideal experimental test bed for the study of multifrequency nonlinear interactions in optical fiber waveguides. Full spatiospectral transparency is experimentally obtained over a 20 nm x 20 km window.

Grading of corneal transparency

Aim: To examine the academic literature on the grading of corneal transparency and to assess the potential use of objective image analysis. Method: Reference databases of academic literature were searched and relevant manuscripts reviewed. Annunziato, Efron (Millennium Edition) and Vistakon-Synoptik corneal oedema grading scale images were analysed objectively for relative intensity, edges detected, variation in intensity and maximum intensity. In addition, corneal oedema was induced in one subject using a low oxygen transmissibility (Dk/t) hydrogel contact lens worn for 3 hours under a light eye patch. Recovery from oedema was monitored over time using ultrasound pachymetry, high and low contrast visual acuity measures, bulbar hyperaemia grading and transparency image analysis of the test and control eyes. Results: Several methods for assessing corneal transparency are described in the academic literature, but none have gained widespread in clinical practice. The change in objective image analysis with printed scale grade was best described by quadratic parametric or sigmoid 3-parameter functions. ‘Pupil image scales’ (Annunziato and Vistakon-Synoptik) were best correlated to average intensity; however, the corneal section scale (Efron) was strongly correlated to variations in intensity. As expected, patching an eye wearing a low Dk/t hydrogel contact lens caused a significant (F=119.2, P<0.001) 14.3% increase in corneal thickness, which gradually recovered under open eye conditions. Corneal section image analysis was the most affected parameter and intensity variation across the slit width, in isolation, was the strongest correlate, accounting for 85.8% of the variance with time following patching, and 88.7% of the variance with corneal thickness. Conclusion: Corneal oedema is best determined objectively by the intensity variation across the width of a corneal section. This can be easily measured using a slit-lamp camera connected to a computer. Oedema due to soft contact lens wear is not easily determined over the pupil area by sclerotic scatter illumination techniques.