Stability analysis and implementation of Power-Hardware-in-the-Loop for power system testing

This project develops the required guidelines to assure stable and accurate operation of Power-Hardware-in-the-Loop implementations. The proposals of this research have been theoretically analyzed and practically examined using a Real-Time Digital Simulator. In this research, the interaction between software simulated power network and the physical power system has been studied. The conditions for different operating regimes have been derived and the corresponding analyses have been presented.

Applying digital product memories in industrial production

Industrial production and supply chains face increased demands for mass customization and tightening regulations on the traceability of goods, leading to higher requirements concerning flexibility, adaptability, and transparency of processes. Technologies for the ’Internet of Things' such as smart products and semantic representations pave the way for future factories and supply chains to fulfill these challenging market demands. In this chapter a backend-independent approach for information exchange in open-loop production processes based on Digital Product Memories DPMs is presented. By storing order-related data directly on the item, relevant lifecycle information is attached to the product itself. In this way, information handover between several stages of the value chain with focus on the manufacturing phase of a product has been realized. In order to report best practices regarding the application of DPM in the domain of industrial production, system prototype implementations focusing on the use case of producing and handling a smart drug case are illustrated.

A new single-phase frequency adaptive Phase-Locked Loop (PLL) for harmonic measurement

The paper presents an improved Phase-Locked Loop (PLL) for measuring the fundamental frequency and selective harmonic content of a distorted signal. This information can be used by grid interfaced devices and harmonic compensators. The single-phase structure is based on the Synchronous Reference Frame (SRF) PLL. The proposed PLL needs only a limited number of harmonic stages by incorporating Moving Average Filters (MAF) for eliminating the undesired harmonic content at each stage. The frequency dependency of MAF in effective filtering of undesired harmonics is also dealt with by a proposed method for adaptation to frequency variations of input signal. The method is suitable for high sampling rates and a wide frequency measurement range. Furthermore, an extended model of this structure is proposed which includes the response to both the frequency and phase angle variations. The proposed algorithm is simulated and verified using Hardware-in-the-Loop (HIL) testing.

FPGA based digital platform for the control of AC drives

This paper presents the new trend of FPGA (Field programmable Gate Array) based digital platform for the control of power electronic systems. There is a rising interest in using digital controllers in power electronic applications as they provide many advantages over their analog counterparts. A board comprising of Cyclone device EP1C12Q240C8 of Altera is used for developing this platform. The details of this board are presented. This developed platform can be used for the controller applications such as UPS, Induction Motor drives and front end converters. A real time simulation of a system can also be done. An open-loop induction motor drive has been implemented using this board and experimental results are presented.

Programmable digital signal averager.

A high speed digital signal averager with programmable features for the sampling period, for the number of channels and for the number of sweeps is described. The system implements a stable averaging algorithm (Deadroff and Trimble 1968) to provide a stable, calibrated display. The performance of the instrument has been evaluated for the reduction of random noise and for comb-filter action. Special uses of the instrument as a box-car integrator and as a transient recorder are also indicated.

Citizens breaking out of filter bubbles: Urban screens as civic media

Social media platforms risk polarising public opinions by employing proprietary algorithms that produce filter bubbles and echo chambers. As a result, the ability of citizens and communities to engage in robust debate in the public sphere is diminished. In response, this paper highlights the capacity of urban interfaces, such as pervasive displays, to counteract this trend by exposing citizens to the socio-cultural diversity of the city. Engagement with different ideas, networks and communities is crucial to both innovation and the functioning of democracy. We discuss examples of urban interfaces designed to play a key role in fostering this engagement. Based on an analysis of works empirically-grounded in field observations and design research, we call for a theoretical framework that positions pervasive displays and other urban interfaces as civic media. We argue that when designed for more than wayfinding, advertisement or television broadcasts, urban screens as civic media can rectify some of the pitfalls of social media by allowing the polarised user to break out of their filter bubble and embrace the cultural diversity and richness of the city.

Fracture Properties of Concrete-Concrete Interfaces Using Digital Image Correlation

The mode I and mode II fracture toughness and the critical strain energy release rate for different concrete-concrete jointed interfaces are experimentally determined using the Digital Image Correlation technique. Concrete beams having different compressive strength materials on either side of a centrally placed vertical interface are prepared and tested under three-point bending in a closed loop servo-controlled testing machine under crack mouth opening displacement control. Digital images are captured before loading (undeformed state) and at different instances of loading. These images are analyzed using correlation techniques to compute the surface displacements, strain components, crack opening and sliding displacements, load-point displacement, crack length and crack tip location. It is seen that the CMOD and vertical load-point displacement computed using DIC analysis matches well with those measured experimentally.

In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Integrated higher-order pulse-width modulation filter-transformer structure for single-phase static compensator

A power filter is necessary to connect the output of a power converter to the grid so as to reduce the harmonic distortion introduced in the line current and voltage by the power converter. Many a times, a transformer is also present before the point of common coupling. Magnetic components often constitute a significant part of the overall weight, size and cost of the grid interface scheme. So, a compact inexpensive design is desirable. A higher-order LCL-filter and a transformer are increasingly being considered for grid interconnection of the power converter. This study proposes a design method based on a three-winding transformer, that generates an integrated structure that behaves as an LCL-filter, with both the filter inductances and the transformer that are merged into a single electromagnetic component. The parameters of the transformer are derived analytically. It is shown that along with a filter capacitor, the transformer parameters provide the filtering action of an LCL-filter. A single-phase full-bridge power converter is operated as a static compensator for performance evaluation of the integrated filter transformer. A resonant integrator-based single-phase phase locked loop and stationary frame AC current controller are employed for grid frequency synchronisation and line current control, respectively.

Signal tracking approach for phase estimation in digital holographic interferometry

In this research work, we introduce a novel approach for phase estimation from noisy reconstructed interference fields in digital holographic interferometry using an unscented Kalman filter. Unlike conventionally used unwrapping algorithms and piecewise polynomial approximation approaches, this paper proposes, for the first time to the best of our knowledge, a signal tracking approach for phase estimation. The state space model derived in this approach is inspired from the Taylor series expansion of the phase function as the process model, and polar to Cartesian conversion as the measurement model. We have characterized our approach by simulations and validated the performance on experimental data (holograms) recorded under various practical conditions. Our study reveals that the proposed approach, when compared with various phase estimation methods available in the literature, outperforms at lower SNR values (i.e., especially in the range 0-20 dB). It is demonstrated with experimental data as well that the proposed approach is a better choice for estimating rapidly varying phase with high dynamic range and noise. (C) 2014 Optical Society of America

All Digital Energy Sensing for Minimum Energy Tracking

Minimizing energy consumption is of utmost importance in an energy starved system with relaxed performance requirements. This brief presents a digital energy sensing method that requires neither a constant voltage reference nor a time reference. An energy minimizing loop uses this to find the minimum energy point and sets the supply voltage between 0.2 and 0.5 V. Energy savings up to 1275% over existing minimum energy tracking techniques in the literature is achieved.

A controller design method for 3 phase 4 wire grid connected VSI with LCL filter

Closed loop control of a grid connected VSI requires line current control and dc bus voltage control. The closed loop system comprising PR current controller and grid connected VSI with LCL filter is a higher order system. Closed loop control gain expressions are therefore difficult to obtain directly for such systems. In this work a simplified approach has been adopted to find current and voltage controller gain expressions for a 3 phase 4 wire grid connected VSI with LCL filter. The closed loop system considered here utilises PR current controller in natural reference frame and PI controller for dc bus voltage control. Asymptotic frequency response plot and gain bandwidth requirements of the system have been used for current control and voltage controller design. A simplified lower order model, derived for closed loop current control, is used for the dc bus voltage controller design. The adopted design method has been verified through experiments by comparison of the time domain response.

Fixed-lag blind equalization and sequence estimation in digital communications systems using sequential importance sampling

We present methods for fixed-lag smoothing using Sequential Importance sampling (SIS) on a discrete non-linear, non-Gaussian state space system with unknown parameters. Our particular application is in the field of digital communication systems. Each input data point is taken from a finite set of symbols. We represent transmission media as a fixed filter with a finite impulse response (FIR), hence a discrete state-space system is formed. Conventional Markov chain Monte Carlo (MCMC) techniques such as the Gibbs sampler are unsuitable for this task because they can only perform processing on a batch of data. Data arrives sequentially, so it would seem sensible to process it in this way. In addition, many communication systems are interactive, so there is a maximum level of latency that can be tolerated before a symbol is decoded. We will demonstrate this method by simulation and compare its performance to existing techniques.