Destruction-free parameter extraction for a physics-based circuit simulator IGCT model

This paper presents a practical destruction-free parameter extraction methodology for a new physics-based circuit simulator buffer-layer Integrated Gate Commutated Thyristor (IGCT) model. Most key parameters needed for this model can be extracted by one simple clamped inductive-load switching experiment. To validate this extraction method, a clamped inductive load switching experiment was performed, and corresponding simulations were carried out by employing the IGCT model with parameters extracted through the presented methodology. Good agreement has been obtained between the experimental data and simulation results.

A CMOS analogue predistortion circuit for wideband optical fibre links

The laser is a major source of nonlinearity for optical fibre communication systems. In this paper, we propose a CMOS analogue predistortion circuit to reduce laser nonlinearity for wideband optical fibre links. The circuit uses a nonlinearity having the inverse transfer characteristic of the directly modulated vertical cavity surface emitting laser (VCSEL). It is shown by post-layout simulation that the predistortion circuit shows 12dBm improvement in the optical fibre system. The optical fibre transmitter front-end with predistortion lineariser is being fabricated using the austriamicrosystems (AMS) 0.3 5μm CMOS technology.

Estimating and Enhancing the Yield of Tuneling SRAM Cells by Simulation

As a novel implementation of the static random access memory (SRAM), the tunneling SRAM (TSRAM) uses the negative differential resistance of tunnel diodes (TD’s) and potentially offers considerable improvements in both standby power dissipation and integration density compared to the conventional CMOS SRAM. TSRAM has not yet been realized with a useful bit capacity mainly because the level of uniformity required of the nanoscale TD’s has been demanding and difficult to achieve. In this letter, we propose a Monte Carlo approach for estimating the yield of TSRAM cells and show that by optimizing the cell’s external circuit parameters, we can relax the allowable tolerance of a key device parameter of a resonant-TD-(RTD) based cell by three times.

FPGA, physics-based modeling of IGBT and pin diode for hardware co-simulation of complex power electronic converters and systems

This paper presents the steps and the challenges for implementing analytical, physics-based models for the insulated gate bipolar transistor (IGBT) and the PIN diode in hardware and more specifically in field programmable gate arrays (FPGAs). The models can be utilised in hardware co-simulation of complex power electronic converters and entire power systems in order to reduce the simulation time without compromising the accuracy of results. Such a co-simulation allows reliable prediction of the system's performance as well as accurate investigation of the power devices' behaviour during operation. Ultimately, this will allow application-specific optimisation of the devices' structure, circuit topologies as well as enhancement of the control and/or protection schemes.

Design and simulation of SMES system using YBCO tapes for direct drive wave energy converters

The ocean represents a huge energy reservoir since waves can be exploited to generate clean and renewable electricity; however, a hybrid energy storage system is needed to smooth the fluctuation. In this paper a hybrid energy storage system using a superconducting magnetic energy system (SMES) and Li-ion battery is proposed. The SMES is designed using Yttrium Barium Copper Oxide (YBCO) tapes, which store 60 kJ electrical energy. The magnet component of the SMES is designed using global optimization algorithm. Mechanical stress, coupled with electromagnetic field, is calculated using COMSOL and Matlab. A cooling system is presented and a suitable refrigerator is chosen to maintain a cold working temperature taking into account four heat sources. Then a microgrid system of direct drive linear wave energy converters is designed. The interface circuit connecting the generator and storage system is given. The result reveals that the fluctuated power from direct drive linear wave energy converters is smoothed by the hybrid energy storage system. The maximum power of the wave energy converter is 10 kW. © 2012 IEEE.

Towards a fast electro-thermo-mechanical IGBT/Diode simulation framework for design of reliable power electronic converters

This paper describes a methodology that enables fast and reasonably accurate prediction of the reliability of power electronic modules featuring IGBTs and p-i-n diodes, by taking into account thermo-mechanical failure mechanisms of the devices and their associated packaging. In brief, the proposed simulation framework performs two main tasks which are tightly linked together: (i) the generation of the power devices' transient thermal response for realistic long load cycles and (ii) the prediction of the power modules' lifetime based on the obtained temperature profiles. In doing so the first task employs compact, physics-based device models, power losses lookup tables and polynomials and combined material-failure and thermal modelling, while the second task uses advanced reliability tests for failure mode and time-to-failure estimation. The proposed technique is intended to be utilised as a design/optimisation tool for reliable power electronic converters, since it allows easy and fast investigation of the effects that changes in circuit topology or devices' characteristics and packaging have on the reliability of the employed power electronic modules. © 2012 IEEE.

A novel modeling approach for design studies of brushless doubly fed induction generator based on magnetic equivalent circuit

Brushless doubly fed induction generator (BDFIG) has substantial benefits, which make it an attractive alternative as a wind turbine generator. However, it suffers from lower efficiency and larger dimensions in comparison to DFIG. Hence, optimizing the BDFIG structure is necessary for enhancing its situation commercially. In previous studies, a simple model has been used in BDFIG design procedure that is insufficiently accurate. Furthermore, magnetic saturation and iron loss are not considered because of difficulties in determination of flux density distributions. The aim of this paper is to establish an accurate yet computationally fast model suitable for BDFIG design studies. The proposed approach combines three equivalent circuits including electric, magnetic and thermal models. Utilizing electric equivalent circuit makes it possible to apply static form of magnetic equivalent circuit, because the elapsed time to reach steady-state results in the dynamic form is too long for using in population-based design studies. The operating characteristics, which are necessary for evaluating the objective function and constraints values of the optimization problem, can be calculated using the presented approach considering iron loss, saturation, and geometrical details. The simulation results of a D-180 prototype BDFIG are compared with measured data in order to validate the developed model. © 1986-2012 IEEE.

Local lifetime engineering in 600V pin diode using mix-mode simulation

This paper reports a detailed analysis of the effect of local lifetime killing (LLK) within the drift region on the reverse recovery (RR) characteristics and on-state performance of 600V Silicon PiN diodes. The paper also discusses the influence of the measurement circuit on the reverse recovery of the high voltage diodes and it proposes a simple and effective mix-mode simulation tool for an accurate assessment of the diode performance in reverse recovery mode. © 2013 IEEE.

Computer simulation of a-Si : H/mu c-Si : H diphasic silicon solar cells

Based on our experimental research on diphasic silicon films, the parameters such as absorption coefficient, mobility lifetime product and bandgap were estimated by means of effective-medium theory. And then computer simulation of a-Si: H/mu c-Si: H diphasic thin film solar cells was performed. It was shown that the more crystalline fraction in the diphasic silicon films, the higher short circuit density, the lower open-circuit voltage and the lower efficiency. From the spectral response, we can see that the response in long wave region was improved significantly with increasing crystalline fraction in the silicon films. Taking Lambertian back refraction into account, the diphasic silicon films with 40%-50% crystalline fraction was considered to be the best intrinsic layer for the bottom solar cell in micromorph tandem.

Numerical simulation of nc-Si : H/c-Si heterojunction solar cells

AMPS simulator, which was developed by Pennsylvania State University, has been used to simulate photovoltaic performances of nc-Si:H/c-Si solar cells. It is shown that interface states are essential factors prominently influencing open circuit voltages (V-OC) and fill factors (FF) of these structured solar cells. Short circuit current density (J(SC)) or spectral response seems more sensitive to the thickness of intrinsic a-Si:H buffer layers inserted into n(+)-nc-Si:H layer and p-c-Si substrates. Impacts of bandgap offset on solar cell performances have also been analyzed. As DeltaE(C) increases, degradation of VOC and FF owing to interface states are dramatically recovered. This implies that the interface state cannot merely be regarded as carrier recombination centres, and impacts of interfacial layer on devices need further investigation. Theoretical maximum efficiency of up to 31.17% (AM1.5,100mW/cm(2), 0.40-1.1mum) has been obtained with BSF structure, idealized light-trapping effect(R-F=0, R-B=1) and no interface states.

Operational Optimization of GaN Thin Film Growth Employing Numerical Simulation in a Showerhead MOCVD Reactor

A detailed reaction-tran sport model was studied in a showerhead reactor for metal organic chemical vapor deposition of GaN film by using computational fluid dynamics simulation. It was found that flat flow lines without swirl are crucial to improve the uniformity of the film growth, and thin temperature gradient above the suscptor can increase the film deposition rate. By above-mentioned research, we can employ higher h (the distance from the susceptor to the inlet), P (operational pressure) and the rate of susceptor rotation to improve the film growth.

Monolithic Integration of Light Emitting Diodes, Photodetector and Receiver Circuit in Standard CMOS Technology

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 mu m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5V 10mA. The silicon dioxide waveguide is composed of multiple layers of silicon dioxide between different metals layers. A two PN-junctions photodetector composed of n-well/p-substrate junction and p(+) active implantation/n-well junction maximizes the depletion region width. The readout circuitry in pixels is exploited to handle as small as 0.1nA photocurrent. Simulation and testing results show that the optical emissions powers are about two orders higher than the low frequency detectivity of silicon CMOS photodetcctor and receiver circuit.

Simulation and fabrication of the SiC-based clamped-clamped filter

In this paper, the SiC-based clamped-clamped filter was designed and fabricated. The filter was composed of two clamped-clamped beam micromechanical resonators coupled by a spring coupling beam. Structural geometries, including the length and width of the resonator beam and coupling beam, were optimized by simulation for high frequency and high Q, under the material properties of SiC. The vibrating modes for the designed filter structure were analyzed by finite element analysis (FEA) method. For the optimized structure, the geometries of resonator beams and coupling beams, as well as the coupling position, the SiC-based clamped-clamped filter was fabricated by surface micromaching technology.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.

Simulation of a monolithically integrated CMOS bioamplifier for EEG recordings

A monolithically integrated CMOS bioamplifier is presented in this paper for EEG recording applications. The capacitive-coupled circuit input structure is utilized to eliminate the large and random DC offsets existing in the electrode-tissue interface. Diode-connected NMOS transistors with negative voltage between gate and source are candidates for large resistors necessary to the bioamplifier. A passive BEF (Band Eliminator Filter) can reduce 50 Hz noise disturbance strength by more than 60 dB. A novel analysis approach is given to help determine the noise power spectral density. Simulation results show that the two-stage CMOS bioamplifier in a closed-loop capacitive feedback configuration,provides an AC in-band gain of 39.6 dB, a DC gain of zero, and an input-referred noise of 87 nVrms integrated from 0.01 Hz to 100 Hz.