Performance evaluation of detectors for digital radiography

To date the hospital radiological workflow is completing a transition from analog to digital technology. Since the X-rays digital detection technologies have become mature, hospitals are trading on the natural devices turnover to replace the conventional screen film devices with digital ones. The transition process is complex and involves not just the equipment replacement but also new arrangements for image transmission, display (and reporting) and storage. This work is focused on 2D digital detector’s characterization with a concern to specific clinical application; the systems features linked to the image quality are analyzed to assess the clinical performances, the conversion efficiency, and the minimum dose necessary to get an acceptable image. The first section overviews the digital detector technologies focusing on the recent and promising technological developments. The second section contains a description of the characterization methods considered in this thesis categorized in physical, psychophysical and clinical; theory, models and procedures are described as well. The third section contains a set of characterizations performed on new equipments that appears to be some of the most advanced technologies available to date. The fourth section deals with some procedures and schemes employed for quality assurance programs.

Numerical Modelling of Graphene Nanoribbon-fets for Analog and Digital Applications

Graphene, that is a monolayer of carbon atoms arranged in a honeycomb lattice, has been isolated only recently from graphite. This material shows very attractive physical properties, like superior carrier mobility, current carrying capability and thermal conductivity. In consideration of that, graphene has been the object of large investigation as a promising candidate to be used in nanometer-scale devices for electronic applications. In this work, graphene nanoribbons (GNRs), that are narrow strips of graphene, for which a band-gap is induced by the quantum confinement of carriers in the transverse direction, have been studied. As experimental GNR-FETs are still far from being ideal, mainly due to the large width and edge roughness, an accurate description of the physical phenomena occurring in these devices is required to have valuable predictions about the performance of these novel structures. A code has been developed to this purpose and used to investigate the performance of 1 to 15-nm wide GNR-FETs. Due to the importance of an accurate description of the quantum effects in the operation of graphene devices, a full-quantum transport model has been adopted: the electron dynamics has been described by a tight-binding (TB) Hamiltonian model and transport has been solved within the formalism of the non-equilibrium Green's functions (NEGF). Both ballistic and dissipative transport are considered. The inclusion of the electron-phonon interaction has been taken into account in the self-consistent Born approximation. In consideration of their different energy band-gap, narrow GNRs are expected to be suitable for logic applications, while wider ones could be promising candidates as channel material for radio-frequency applications.

Low Correlated Sequences & Architectures and Algorithms for Analog-to-Information Converters: Theory, Design, Implementation and Applications.

Most electronic systems can be described in a very simplified way as an assemblage of analog and digital components put all together in order to perform a certain function. Nowadays, there is an increasing tendency to reduce the analog components, and to replace them by operations performed in the digital domain. This tendency has led to the emergence of new electronic systems that are more flexible, cheaper and robust. However, no matter the amount of digital process implemented, there will be always an analog part to be sorted out and thus, the step of converting digital signals into analog signals and vice versa cannot be avoided. This conversion can be more or less complex depending on the characteristics of the signals. Thus, even if it is desirable to replace functions carried out by analog components by digital processes, it is equally important to do so in a way that simplifies the conversion from digital to analog signals and vice versa. In the present thesis, we have study strategies based on increasing the amount of processing in the digital domain in such a way that the implementation of analog hardware stages can be simplified. To this aim, we have proposed the use of very low quantized signals, i.e. 1-bit, for the acquisition and for the generation of particular classes of signals.

Ultra low power analog-to-information conversion by short-time compressed sensing

Il compressed sensing è un’innovativa tecnica per l’acquisizione dei dati, che mira all'estrazione del solo contenuto informativo intrinseco di un segnale. Ciò si traduce nella possibilità di acquisire informazione direttamente in forma compressa, riducendo la quantità di risorse richieste per tale operazione. In questa tesi è sviluppata un'architettura hardware per l'acquisizione di segnali analogici basata sul compressed sensing, specializzata al campionamento con consumo di potenza ridotto di segnali biomedicali a basse frequenze. Lo studio è svolto a livello di sistema mediante l'integrazione della modulazione richiesta dal compressed sensing in un convertitore analogico-digitale ad approssimazioni successive, modificandone la logica di controllo. Le prestazioni risultanti sono misurate tramite simulazioni numeriche e circuitali. Queste confermano la possibilità di ridurre la complessità hardware del sistema di acquisizione rispetto allo stato dell'arte, senza alterarne le prestazioni.

Digital Control Implementation to Reduce the Cost and Improve the Performance of the Control Stage of an Industrial Switched-Mode Power Supply

The main objective of this work is the design and implementation of the digital control stage of a 280W AC/DC industrial power supply in a single low-cost microcontroller to replace the analog control stage. The switch-mode power supply (SMPS) consists of a PFC boost converter with fixed frequency operation and a variable frequency LLC series resonant DC/DC converter. Input voltage range is 85VRMS-550VRMS and the output voltage range is 24V-28V. A digital controller is especially suitable for this kind of SMPS to implement its multiple functionalities and to keep the efficiency and the performance high over the wide range of input voltages. Additional advantages of the digital control are reliability and size. The optimized design and implementation of the digital control stage it is presented. Experimental results show the stable operation of the controlled system and an estimation of the cost reduction achieved with the digital control stage.

Synchronizing chaotic optically-programmable digital circuits

In this paper an approach to the synchronization of chaotic circuits has been reported. It is based on an optically programmable logic cell and the signals involved are fully digital. It is based on the reception of the same input signal on sender and receiver and from this approach, with a posterior correlation between both outputs, an identical chaotic output is obtained in both systems. No conversion from analog to digital signals is needed. The model here presented is based on a computer simulation.

High yield conversion of doxorubicin to 2-pyrrolinodoxorubicin, an analog 500-1000 times more potent: structure-activity relationship of daunosamine-modified derivatives of doxorubicin.

A convenient, high yield conversion of doxorubicin to 3'-deamino-3'-(2''-pyrroline-1''-yl)doxorubicin is described. This daunosamine-modified analog of doxorubicin is 500-1000 times more active in vitro than doxorubicin. The conversion is effected by using a 30-fold excess of 4-iodobutyraldehyde in anhydrous dimethylformamide. The yield is higher than 85%. A homolog of this compound, 3'-deamino-3'-(1'',3''-tetrahydropyridine-1''-yl)doxorubicin, was also synthesized by using 5-iodovaleraldehyde. In this homolog, the daunosamine nitrogen is incorporated into a six- instead of a five-membered ring. This analog was 30-50 times less active than its counterpart with a five-membered ring. A similar structure-activity relationship was found when 3'-deamino-3'-(3''-pyrrolidone-1''-yl)doxorubicin (containing a five-membered ring) and 3'-deamino-3'-(3''-piperidone-1''-yl)doxorubicin (with a six-membered ring) were tested in vitro, the former being 5 times more potent than the latter. To further elucidate structure-activity relationships, 3'-deamino-3'-(pyrrolidine-1''-yl)doxorubicin, 3'-deamino-3'-(isoindoline-2''-yl)doxorubicin, 3'-deamino-3'-(2''-methyl-2''-pyrroline-1''-yl)doxorubicin, and 3'-deamino-3'-(3''-pyrroline-1''-yl)doxorubicin were also synthesized and tested. All the analogs were prepared by using reactive halogen compounds for incorporating the daunosamine nitrogen of doxorubicin into a five- or six-membered ring. These highly active antineoplastic agents can be used for incorporation into targeted cytotoxic analogs of luteinizing hormone-releasing hormone intended for cancer therapy.

Conversion of a digital camera into a non-contact colorimeter for use in stone cultural heritage: The application case to Spanish granites

In this study, a digital CMOS camera was calibrated for use as a non-contact colorimeter for measuring the color of granite artworks. The low chroma values of the granite, which yield similar stimulation of the three color channels of the camera, proved to be the most challenging aspect of the task. The appropriate parameters for converting the device-dependent RGB color space into a device-independent color space were established. For this purpose, the color of a large number of Munsell samples (corresponding to the previously defined color gamut of granite) was measured with a digital camera and with a spectrophotometer (reference instrument). The color data were then compared using the CIELAB color formulae. The best correlations between measurements were obtained when the camera works to 10-bits and the spectrophotometric measures in SCI mode. Finally, the calibrated instrument was used successfully to measure the color of six commercial varieties of Spanish granite.

Performance of the analog and the digital profilometer with wheels and with non-contract transducers. Final report.

Texas State Department of Highways and Public Transportation, Transportation Planning Division, Austin

Design Strategies and Modelling of Low-Power Sigma-Delta Analog-to-Digital Converters

Oggi, i dispositivi portatili sono diventati la forza trainante del mercato consumer e nuove sfide stanno emergendo per aumentarne le prestazioni, pur mantenendo un ragionevole tempo di vita della batteria. Il dominio digitale è la miglior soluzione per realizzare funzioni di elaborazione del segnale, grazie alla scalabilità della tecnologia CMOS, che spinge verso l'integrazione a livello sub-micrometrico. Infatti, la riduzione della tensione di alimentazione introduce limitazioni severe per raggiungere un range dinamico accettabile nel dominio analogico. Minori costi, minore consumo di potenza, maggiore resa e una maggiore riconfigurabilità sono i principali vantaggi dell'elaborazione dei segnali nel dominio digitale. Da più di un decennio, diverse funzioni puramente analogiche sono state spostate nel dominio digitale. Ciò significa che i convertitori analogico-digitali (ADC) stanno diventando i componenti chiave in molti sistemi elettronici. Essi sono, infatti, il ponte tra il mondo digitale e analogico e, di conseguenza, la loro efficienza e la precisione spesso determinano le prestazioni globali del sistema. I convertitori Sigma-Delta sono il blocco chiave come interfaccia in circuiti a segnale-misto ad elevata risoluzione e basso consumo di potenza. I tools di modellazione e simulazione sono strumenti efficaci ed essenziali nel flusso di progettazione. Sebbene le simulazioni a livello transistor danno risultati più precisi ed accurati, questo metodo è estremamente lungo a causa della natura a sovracampionamento di questo tipo di convertitore. Per questo motivo i modelli comportamentali di alto livello del modulatore sono essenziali per il progettista per realizzare simulazioni veloci che consentono di identificare le specifiche necessarie al convertitore per ottenere le prestazioni richieste. Obiettivo di questa tesi è la modellazione del comportamento del modulatore Sigma-Delta, tenendo conto di diverse non idealità come le dinamiche dell'integratore e il suo rumore termico. Risultati di simulazioni a livello transistor e dati sperimentali dimostrano che il modello proposto è preciso ed accurato rispetto alle simulazioni comportamentali.

Asynchronous digital optical regenerator for 4 x 40 Gbit/s WDM to 160 Gbit/s OTDM conversion

We propose and numerically analyse an asynchronous digital optical regenerator using a single-EAM loop and a novel neighbor-combine approach. It effectively re-synchronizes input signals with arbitrary phases to the local clock, and regenerates signals with high amplitude fluctuation and polarization mode dispersion. We demonstrate the application of this regenerator for 4 x 40 Gbit/s WDM to 160 Gbit/s OTDM conversion.

Asynchronous digital optical regenerator for 4 x 40 Gbit/s WDM to 160 Gbit/s OTDM conversion

We propose and numerically analyse an asynchronous digital optical regenerator using a single-EAM loop and a novel neighbor-combine approach. It effectively re-synchronizes input signals with arbitrary phases to the local clock, and regenerates signals with high amplitude fluctuation and polarization mode dispersion. We demonstrate the application of this regenerator for 4 x 40 Gbit/s WDM to 160 Gbit/s OTDM conversion.

Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.