Photocatalytic and photovoltaic activities of TiO2 architectures with dominant {001} facets

Titanium dioxide is one of the most basic materials in our daily life, which has emerged as an excellent photocatalyst material for environmental purification and photovoltaic material working in dye-sensitized solar cell. We present two types of TiO2 architectures which are constructed by plates and sheets, respectively, and both subunits are dominant with {001} facets. The photocatalytic degradation of methyl orange in UV/supported-TiO2 systems was investigated and the mechanism was discussed. The experimental results show that photocatalytic degradation rate is favoured by larger surface area. The sheet structure shows superior photocatalytic activity than plate structure. Moreover, the materials with sheet structure were also used to investigate the photovoltaic property. The power conversion efficiency is 7.57%, indicating the materials with this unique structure are excellent in photocatalytic and photovoltaic applications.

Introduction to the special issue on next generation network architectures, protocols, theory, systems and applications

This special issue of Networking Science focuses on Next Generation Network (NGN) that enables the deployment of access independent services over converged fixed and mobile networks. NGN is a packet-based network and uses the Internet protocol (IP) to transport the various types of traffic (voice, video, data and signalling). NGN facilitates easy adoption of distributed computing applications by providing high speed connectivity in a converged networked environment. It also makes end user devices and applications highly intelligent and efficient by empowering them with programmability and remote configuration options. However, there are a number of important challenges in provisioning next generation network technologies in a converged communication environment. Some preliminary challenges include those that relate to QoS, switching and routing, management and control, and security which must be addressed on an urgent or emergency basis. The consideration of architectural issues in the design and pro- vision of secure services for NGN deserves special attention and hence is the main theme of this special issue.

Design methodologies and architectures of hardware-based evolutionary algorithms for aerospace optimisation applications on FPGAS

This thesis is a study of new design methods for allowing evolutionary algorithms to be more effectively utilised in aerospace optimisation applications where computation needs are high and computation platform space may be restrictive. It examines the applicability of special hardware computational platforms known as field programmable gate arrays and shows that with the right implementation methods they can offer significant benefits. This research is a step forward towards the advancement of efficient and highly automated aircraft systems for meeting compact physical constraints in aerospace platforms and providing effective performance speedups over traditional methods.

Domain-specific application analysis for customized instruction identification

With the increasing importance of Application Domain Specific Processor (ADSP) design, a significant challenge is to identify special-purpose operations for implementation as a customized instruction. While many methodologies have been proposed for this purpose, they all work for a single algorithm chosen from the target application domain. Such algorithm-specific approaches are not suitable for designing instruction sets applicable to a whole family of related algorithms. For an entire range of related algorithms, this paper develops a methodology for identifying compound operations, as a basis for designing “domain-specific” Instruction Set Architectures (ISAs) that can efficiently run most of the algorithms in a given domain. Our methodology combines three different static analysis techniques to identify instruction sequences common to several related algorithms: identification of (non-branching) instruction sequences that occur commonly across the algorithms; identification of instruction sequences nested within iterative constructs that are thus executed frequently; and identification of commonly-occurring instruction sequences that span basic blocks. Choosing different combinations of these results enables us to design domain-specific special operations with different desired characteristics, such as performance or suitability as a library function. To demonstrate our approach, case studies are carried out for a family of thirteen string matching algorithms. Finally, the validity of our static analysis results is confirmed through independent dynamic analysis experiments and performance improvement measurements.

Exploitation of the menshutkin reaction for the controlled assembly of halogen bonded architectures incorporating 1,2-diiodotetrafluorobenzene and 1,3,5-Triiodotrifluorobenzene

1,4-Diazabicyclo[2.2.2]octane (DABCO) forms well-defined co-crystals with 1,2-diiodotetrafluorobenzene (1,2-DITFB), [(1,2-DITFB)2DABCO], and 1,3,5-triiodotrifluorobenzene, [(1,3,5-TITFB)2DABCO]. Both systems exhibited lower-than-expected supramolecular connectivity, which inspired a search for polymorphs in alternative crystallization solvents. In dichloromethane solution, the Menshutkin reaction was found to occur, generating chloride anions and quaternary ammonium cations through the reaction between the solvent and DABCO. The controlled in situ production of chloride ions facilitated the crystallization of new halogen bonded networks, DABCO–CH2Cl[(1,2-DITFB)Cl] (zigzag X-bonded chains) and (DABCO–CH2Cl)3[(1,3,5-TITFB)2Cl3]·CHCl3 (2D pseudo-trigonal X-bonded nets displaying Borremean entanglement), propagating with charge-assisted C–I···Cl– halogen bonds. The method was found to be versatile, and substitution of DABCO with triethylamine (TEA) gave (TEA-CH2Cl)3[(1,2-DITFB)Cl3]·4(H2O) (mixed halogen bond hydrogen bond network with 2D supramolecular connectivity) and TEA-CH2Cl[(1,3,5-TITFB)Cl] (tightly packed planar trigonal nets). The co-crystals were typically produced in high yield and purity with relatively predictable supramolecular topology, particularly with respect to the connectivity of the iodobenzene molecules. The potential to use this synthetic methodology for crystal engineering of halogen bonded architectures is demonstrated and discussed.

Synthesis of novel interlocked architectures in solution and solid phase

Mechanically interlocked molecules, such as catenanes and rotaxanes, are fascinating due to their unique sensing and catalytic properties and their potential to act as molecular motors or switches. Traditionally their synthesis has been laborious and expensive, however this research project endeavoured to overcome this challenge by exploring novel ways of preparing mechanically interlocked molecules both in solution and on surfaces. A series of disulfide-linked macrocycles, [2]catenanes and [2]rotaxanes were synthesised in solution using reversible dynamic covalent chemistry. Subsequently, the interlocked architectures were adapted into solid-tethered systems via attachment to swelling polystyrene resins.

Designs and architectures for the next generation of organic solar cells

Organic solar cells show great promise as an economically and environmentally friendly technology to utilize solar energy because of their simple fabrication processes and minimal material usage. However, new innovations and breakthroughs are needed for organic solar cell technology to become competitive in the future. This article reviews research efforts and accomplishments focusing on three issues: power conversion efficiency, device stability and processability for mass production, followed by an outlook for optimizing OSC performance through device engineering and new architecture designs to realize next generation organic solar cells.

Scalable and flexible large display arrays: A novel approach to the architectural enhancement of a prototype large display array

Large Display Arrays (LDAs) use Light Emitting Diodes (LEDs) in order to inform a viewing audience. A matrix of individually driven LEDs allows the area represented to display text, images and video. LDAs have undergone rapid development over the past 10 years in both the modular and semi-flexible formats. This thesis critically analyses the communication architecture and processor functionality of current LDAs and presents an alternative method, that is, Scalable Flexible Large Display Arrays (SFLDAs). SFLDAs are more adaptable to a variety of applications because of enhancements in scalability and flexibility. Scalability is the ability to configure SFLDAs from 0.8m2 to 200m2. Flexibility is increased functionality within the processors to handle changes in configuration and the use of a communication architecture that standardises two-way communication throughout the SFLDA. While common video platforms such as Digital Video Interface (DVI), Serial Digital Interface (SDI), and High Definition Multimedia Interface (HDMI) are considered as solutions for the communication architecture of SFLDAs, so too is modulation, fibre optic, capacitive coupling and Ethernet. From an analysis of these architectures, Ethernet was identified as the best solution. The use of Ethernet as the communication architecture in SFLDAs means that both hardware and software modules are capable of interfacing to the SFLDAs. The Video to Ethernet Processor Unit (VEPU), Scoreboard, Image and Control Software (SICS) and Ethernet to LED Processor Unit (ELPU) have been developed to form the key components in designing and implementing the first SFLDA. Data throughput rate and spectrophotometer tests were used to measure the effectiveness of Ethernet within the SFLDA constructs. The result of testing and analysis of these architectures showed that Ethernet satisfactorily met the requirements of SFLDAs.

Implementation of Art1 and Art2 Artificial Neural Networks on Ring and Mesh Architectures

The Artificial Neural Networks (ANNs) are being used to solve a variety of problems in pattern recognition, robotic control, VLSI CAD and other areas. In most of these applications, a speedy response from the ANNs is imperative. However, ANNs comprise a large number of artificial neurons, and a massive interconnection network among them. Hence, implementation of these ANNs involves execution of computer-intensive operations. The usage of multiprocessor systems therefore becomes necessary. In this article, we have presented the implementation of ART1 and ART2 ANNs on ring and mesh architectures. The overall system design and implementation aspects are presented. The performance of the algorithm on ring, 2-dimensional mesh and n-dimensional mesh topologies is presented. The parallel algorithm presented for implementation of ART1 is not specific to any particular architecture. The parallel algorithm for ARTE is more suitable for a ring architecture.

Simultaneous display of spectrum and image in a single plane, and the realization of a lensless coherent optical processor

A novel method, designated the holographic spectrum reconstruction (HSR) method, is proposed for achieving simultaneous display of the spectrum and image of an object in a single plane. A study of the scaling behaviour of both the spectrum and the image has been carried out and based on this study, it is demonstrated that a lensless coherent optical processor can be realized.

Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures

In this paper we develop compilation techniques for the realization of applications described in a High Level Language (HLL) onto a Runtime Reconfigurable Architecture. The compiler determines Hyper Operations (HyperOps) that are subgraphs of a data flow graph (of an application) and comprise elementary operations that have strong producer-consumer relationship. These HyperOps are hosted on computation structures that are provisioned on demand at runtime. We also report compiler optimizations that collectively reduce the overheads of data-driven computations in runtime reconfigurable architectures. On an average, HyperOps offer a 44% reduction in total execution time and a 18% reduction in management overheads as compared to using basic blocks as coarse grained operations. We show that HyperOps formed using our compiler are suitable to support data flow software pipelining.

Parallel processor scheduling for minimizing total weighted tardiness using ant colony optimization

In the modern business environment, meeting due dates and avoiding delay penalties are very important goals that can be accomplished by minimizing total weighted tardiness. We consider a scheduling problem in a system of parallel processors with the objective of minimizing total weighted tardiness. Our aim in the present work is to develop an efficient algorithm for solving the parallel processor problem as compared to the available heuristics in the literature and we propose the ant colony optimization approach for this problem. An extensive experimentation is conducted to evaluate the performance of the ACO approach on different problem sizes with the varied tardiness factors. Our experimentation shows that the proposed ant colony optimization algorithm is giving promising results compared to the best of the available heuristics.

Rational design of 3D dendritic TiO2 nanostructures with favorable architectures

Controlling the morphology and size of titanium dioxide (TiO2) nanostructures is crucial to obtain superior photocatalytic, photovoltaic, and electrochemical properties. However, the synthetic techniques for preparing such structures, especially those with complex configurations, still remain a challenge because of the rapid hydrolysis of Ti-containing polymer precursors in aqueous solution. Herein, we report a completely novel approach-three- dimensional (3D) TiO2 nanostructures with favorable dendritic architectures-through a simple hydrothermal synthesis. The size of the 3D TiO2 dendrites and the morphology of the constituent nano-units, in the form of nanorods, nanoribbons, and nanowires, are controlled by adjusting the precursor hydrolysis rate and the surfactant aggregation. These novel configurations of TiO2 nanostructures possess higher surface area and superior electrochemical properties compared to nanoparticles with smooth surfaces. Our findings provide an effective solution for the synthesis of complex TiO2 nano-architectures, which can pave the way to further improve the energy storage and energy conversion efficiency of TiO 2-based devices.

A Petri net model for evaluating packet buffering strategies in a network processor

Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri net model of IP forwarding application on IXP2400 that models the different levels of the memory hierarchy. The cell based interface used to receive and transmit packets in a network processor leads to some small size DRAM accesses. Such narrow accesses to the DRAM expose the bank access latency, reducing the bandwidth that can be realized. With real traces up to 30% of the accesses are smaller than the cell size, resulting in 7.7% reduction in DRAM bandwidth. To overcome this problem, we propose buffering these small chunks of data in the on chip scratchpad memory. This scheme also exploits greater degree of parallelism between different levels of the memory hierarchy. Using real traces from the internet, we show that the transmit rate can be improved by an average of 21% over the base scheme without the use of additional hardware. Further, the impact of different traffic patterns on the network processor resources is studied. Under real traffic conditions, we show that the data bus which connects the off-chip packet buffer to the micro-engines, is the obstacle in achieving higher throughput.

Compiler-assisted instruction decoder energy optimization for clustered VLIW architectures

Traditionally, an instruction decoder is designed as a monolithic structure that inhibit the leakage energy optimization. In this paper, we consider a split instruction decoder that enable the leakage energy optimization. We also propose a compiler scheduling algorithm that exploits instruction slack to increase the simultaneous active and idle duration in instruction decoder. The proposed compiler-assisted scheme obtains a further 14.5% reduction of energy consumption of instruction decoder over a hardware-only scheme for a VLIW architecture. The benefits are 17.3% and 18.7% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively.