Control point design using modular logic,

Mode of access: Internet.

Experimental and formal language design applied to control constructs for interactive computing /

Vita.

The delay/re-read protocol for concurrency control in databases /

"UILU-ENG 83 1723"--Cover.

A stochastic control system /

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VIPTRAN2 : an improved programming language and its compiler for process control equations /

Mode of access: Internet.

HEC-1, flood hydrograph package : the Hydrologic Engineering Center computer program 23-X6-L270.

At head of cover title: 23-70. Generalized computer program.

Central flow control software design document.

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Osiris III; an integrated collection of computer programs for the management and analysis of social science data.

v. 1. System and program description.--v. 2. Error Messages.--v. 3. Summary of control cards.--v. 4. Sample jobs.--v. 5. Formulas and statistical references.--v. 6. Primer.

Data Disc control: Graphics 8,

"COO-1469-0152. File no. 818."

Fast nonadiabatic two-qubit gates for the Kane quantum computer

In this paper, we apply the canonical decomposition of two-qubit unitaries to find pulse schemes to control the proposed Kane quantum computer. We explicitly find pulse sequences for the controlled-NOT, swap, square root of swap, and controlled Z rotations. We analyze the speed and fidelity of these gates, both of which compare favorably to existing schemes. The pulse sequences presented in this paper are theoretically faster, with higher fidelity, and simpler. Any two-qubit gate may be easily found and implemented using similar pulse sequences. Numerical simulation is used to verify the accuracy of each pulse scheme.

Voltage control of exchange coupling in phosphorus doped silicon

Motivated by applications to quantum computer architectures we study the change in the exchange interaction between neighbouring phosphorus donor electrons in silicon due to the application of voltage biases to surface control electrodes. These voltage biases create electro-static fields within the crystal substrate, perturbing the states of the donor electrons and thus altering the strength of the exchange interaction between them. We find that control gates of this kind can be used to either enhance or reduce the strength of the interaction, by an amount that depends both on the magnitude and orientation of the donor separation.

Global control and fast solid-state donor electron spin quantum computing

We propose a scheme for quantum information processing based on donor electron spins in semiconductors, with an architecture complementary to the original Kane proposal. We show that a naive implementation of electron spin qubits provides only modest improvement over the Kane scheme, however through the introduction of global gate control we are able to take full advantage of the fast electron evolution timescales. We estimate that the latent clock speed is 100-1000 times that of the nuclear spin quantum computer with the ratio T-2/T-ops approaching the 10(6) level.

A new approach to control of MIMO processes with static nonlinearities using an extended IMC framework

In this paper, a new control design method is proposed for stable processes which can be described using Hammerstein-Wiener models. The internal model control (IMC) framework is extended to accommodate multiple IMC controllers, one for each subsystem. The concept of passive systems is used to construct the IMC controllers which approximate the inverses of the subsystems to achieve dynamic control performance. The Passivity Theorem is used to ensure the closed-loop stability. (c) 2005 Elsevier Ltd. All rights reserved.

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving fitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.