Hybrid LCI/VSI Power Circuit-A Universal High-Power Converter Solution for Wound Field Synchronous Motor Drives

Load commutated inverter (LCI)-fed wound field synchronous motor drives are used for medium-voltage high-power drive applications. This drive suffers from drawbacks such as complex starting procedure, sixth harmonic torque pulsations, quasi square wave motor current, notches in the terminal voltages, etc. In this paper, a hybrid converter circuit, consisting of an LCI and a voltage source inverter (VSI), is proposed, which can be a universal high-power converter solution for wound field synchronous motor drives. The proposed circuit, with the addition of a current-controlled VSI, overcomes nearly all of the shortcomings present in the conventional LCI-based system besides providing many additional advantages. In the proposed drive, the motor voltage and current are always sinusoidal even with the LCI switching at the fundamental frequency. The performance of the drive is demonstrated with detailed experimental waveforms from a 15.8-hp salient pole wound field synchronous machine. Finally, a brief description of the control scheme used for the proposed circuit is given.

A Note On The Effect Of Short And Long Laminar Separation-Bubbles On Desinent Cavitation

Earlier desinent cavitation studies on a 1/8 caliber ogive by one of the authors (J. W. H.) showed a sudden change in the magnitude of the desinent cavitation number at a critical velocity. In the present work it is shown by means of oil-film flow visualization that below the critical velocity a long laminar separation bubble exists whereas above the critical velocity the laminar separation bubble is short. Thus the desinent cavitation characteristics of a 1/8 caliber ogive are governed by the nature of the viscous flow around the body.

Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits

Abstract—A method of testing for parametric faults of analog circuits based on a polynomial representaion of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies apart from DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. The method needs very little augmentation of circuit to make it testable as only output parameters are used for classification. This procedure is shown to uncover several parametric faults causing smaller than 5 % deviations the nominal values. Fault diagnosis based upon sensitivity of polynomial coefficients at relevant frequencies is also proposed.

V-Transform: “An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits

Abstract—DC testing of parametric faults in non-linear analog circuits based on a new transformation, entitled, V-Transform acting on polynomial coefficient expansion of the circuit function is presented. V-Transform serves the dual purpose of monotonizing polynomial coefficients of circuit function expansion and increasing the sensitivity of these coefficients to circuit parameters. The sensitivity of V-Transform Coefficients (VTC) to circuit parameters is up to 3x-5x more than sensitivity of polynomial coefficients. As a case study, we consider a benchmark elliptic filter to validate our method. The technique is shown to uncover hitherto untestable parametric faults whose sizes are smaller than 10 % of the nominal values. I.

Modified Stability Checking for On-Line Error Detection

The paper propose a unified error detection technique, based on stability checking, for on-line detection of delay, crosstalk and transient faults in combinational circuits and SEUs in sequential elements. The proposed method, called modified stability checking (MSC), overcomes the limitations of the earlier stability checking methods. The paper also proposed a novel checker circuit to realize this scheme. The checker is self-checking for a wide set of realistic internal faults including transient faults. Extensive circuit simulations have been done to characterize the checker circuit. A prototype checker circuit for a 1mm2 standard cell array has been implemented in a 0.13mum process.

Modeling of the Effects of Process Variations on Circuit Delay at 65nm

A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.

Towards formal verification of analog mixed signal designs using SPICE circuit simulation traces

An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design, to be also used for validating its different refinements and design implementation; thereby, providing a simple route to formal verification at different levels of implementation. The feasibility of the proposed approach is demonstrated with a case study based on a tunnel diode oscillator. Since the device characteristic of a tunnel diode is highly non-linear with a negative resistance region, dynamic behavior of circuits in which it is employed as an element is difficult to model, analyze and verify within a general hybrid system formal verification tool. In the case study presented the formal model and the proposed computational techniques have been incorporated into CheckMate, a formal verification tool based on MATLAB and Simulink-Stateflow Framework from MathWorks.

Bypass operation in bridge convertors for high-voltage d.c. transmission

Bypass operation with the aid of a special bypass valve is an important part of present-day schemes of protection for h.v. d.c. transmission systems. In this paper, the possibility of using two valves connected to any phase in the bridge convertor for the purpose of bypass operation is studied. The scheme is based on the use of logic circuits in conjunction with modified methods of fault detection. Analysis of the faults in a d.c. transmission system is carried out with the object of determining the requirements of such a logic-circuit control system. An outline of the scheme for the logic-circuit control of the bypass operation for both rectifier and invertor bridges is then given. Finally, conclusions are drawn regarding the advantages of such a system, which include reduction in the number of valves, prevention of severe faults and fast clearance of faults, in addition to the immediate location of the fault and its nature.

Analysis of Natural Half-Wave-Length Power Transmission Lines

This paper provides additional theoretical information on half-wave-length power transmission. The analysis is rendered more general by consideration of a natural half-wave line instead of a short line tuned to half-wave. The effects of line loading and its power factor on the voltage and current profiles of the line and ganerator excitation have been included. Some of the operating problems such as charging of the line and synchronization of the half-wave system are also discussed. The inevitability of power-frequency overvoltages during faults is established. Stability studies have indicated that the use of switching stations is not beneficial. Typical swing curves are also presented.

Amorphous Hydrogenated Silicon: A Perspective on Circuit Synthesis

Abstract | Non-crystalline or glassy semiconductors are of great research interest for the fabrication of large area electronic systems such as displays and image sensors. Good uniformity over large areas, low temperature fabrication and the promise of low cost electronics on large area mechanically flexible and rigid substrates are some attractive features of these technologies. The article focusses on amorphous hydrogenated silicon thin film transistors, and reviews the problems, solutions and applications of these devices.