Rapid design of application specific FFT cores

Methods are presented for developing synthesizable FFT cores. These are based on a modular approach in which parameterized commutator and processor blocks are cascaded to implement the computations required in many important FFT signal flow graphs. In addition, it is shown how the use of a digital serial data organization can be used to produce systems that offer 100% processor utilization along with reductions in storage requirements. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with ones created using manual methods but with significant reductions in design times.

Hardware elliptic curve cryptographic processor over GF(p)

A novel hardware architecture for elliptic curve cryptography (ECC) over GF(p) is introduced. This can perform the main prime field arithmetic functions needed in these cryptosystems including modular inversion and multiplication. This is based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation. The processor described uses a full-word multiplier which requires much fewer clock cycles than previous methods, while still maintaining a competitive critical path delay. The benefits of the approach have been demonstrated by utilizing these techniques to create a field-programmable gate array (FPGA) design. This can perform a 256-bit prime field scalar point multiplication in 3.86 ms, the fastest FPGA time reported to date. The ECC architecture described can also perform four different types of modular inversion, making it suitable for use in many different ECC applications. © 2006 IEEE.

Rapid silicon design of discrete orthonormal wavelet transforms based algorithms

A methodology has been developed which allows a non-specialist to rapidly design silicon wavelet transform cores for a variety of specifications. The cores include both forward and inverse orthonormal wavelet transforms. This methodology is based on efficient, modular and scaleable architectures utilising time-interleaved coefficients for the wavelet transform filters. The cores are parameterized in terms of wavelet type and data and coefficient word lengths. The designs have been captured in VHDL and are hence portable across a range of silicon foundries as well as FPGA and PLD implementations.

Systolic VLSI compiler (SVC) for high performance vector quantisation chips

An overview is given of a systolic VLSI compiler (SVC) tool currently under development for the automated design of high performance digital signal processing (DSP) chips. Attention is focused on the design of systolic vector quantization chips for use in both speech and image coding systems. The software in question consists of a cell library, silicon assemblers, simulators, test pattern generators, and a specially designed graphics shell interface which makes it expandable and user friendly. It allows very high performance digital coding systems to be rapidly designed in VLSI.

Synthesizable FFT cores

Methods are presented for developing synthesizable FFT cores. These are based on a modular approach in which parameterizable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organization with generic commutator blocks to produce systems that offer 100% processor utilization with storage requirements less than previous designs. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with manual methods but with significant reductions in design times.

A low-cost solution for the restoration of femoral head centre during total hip arthroplasty

Restoration of joint centre during total hip arthroplasty is critical. While computer-aided navigation can improve accuracy during total hip arthroplasty, its expense makes it inaccessible to the majority of surgeons. This article evaluates the use, in the laboratory, of a calliper with a simple computer application to measure changes in femoral head centres during total hip arthroplasty. The computer application was designed using Microsoft Excel and used calliper measurements taken pre- and post-femoral head resection to predict the change in head centre in terms of offset and vertical height between the femoral head and newly inserted prosthesis. Its accuracy was assessed using a coordinate measuring machine to compare changes in preoperative and post-operative head centre when simulating stem insertion on 10 sawbone femurs. A femoral stem with a modular neck was used, which meant nine possible head centre configurations were available for each femur, giving 90 results. The results show that using this technique during a simulated total hip arthroplasty, it was possible to restore femoral head centre to within 6?mm for offset (mean 1.67?±?1.16?mm) and vertical height (mean 2.14?±?1.51?mm). It is intended that this low-cost technique be extended to inform the surgeon of a best-fit solution in terms of neck length and neck type for a specific prosthesis.

FPGA Prototyping of Emerging Manycore Architectures for Parallel Programming Research using Formic Boards

Performance evaluation of parallel software and architectural exploration of innovative hardware support face a common challenge with emerging manycore platforms: they are limited by the slow running time and the low accuracy of software simulators. Manycore FPGA prototypes are difficult to build, but they offer great rewards. Software running on such prototypes runs orders of magnitude faster than current simulators. Moreover, researchers gain significant architectural insight during the modeling process. We use the Formic FPGA prototyping board [1], which specifically targets scalable and cost-efficient multi-board prototyping, to build and test a 64-board model of a 512-core, MicroBlaze-based, non-coherent hardware prototype with a full network-on-chip in a 3D-mesh topology. We expand the hardware architecture to include the ARM Versatile Express platforms and build a 520-core heterogeneous prototype of 8 Cortex-A9 cores and 512 MicroBlaze cores. We then develop an MPI library for the prototype and evaluate it extensively using several bare-metal and MPI benchmarks. We find that our processor prototype is highly scalable, models faithfully single-chip multicore architectures, and is a very efficient platform for parallel programming research, being 50,000 times faster than software simulation.

Modification of Fluorescent Photoinduced Electron Transfer (PET) Sensors/Switches To Produce Molecular Photo-Ionic Triode Action

The fluorophore-spacer₁-receptor₁-spacer₂-receptor₂ system (where receptor₂ alone is photoredox-inactive) shows ionically tunable proton-induced fluorescence off-on switching, which is reminiscent of thermionic triode behavior. This also represents a new extension to modular switch systems based on photoinduced electron transfer (PET) towards the emulation of analogue electronic devices.

A spectral synthesis code for rapid modelling of supernovae

We present TARDIS-an open-source code for rapid spectral modelling of supernovae (SNe). Our goal is to develop a tool that is sufficiently fast to allow exploration of the complex parameter spaces of models for SN ejecta. This can be used to analyse the growing number of highquality SN spectra being obtained by transient surveys. The code uses Monte Carlo methods to obtain a self-consistent description of the plasma state and to compute a synthetic spectrum. It has a modular design to facilitate the implementation of a range of physical approximations that can be compared to assess both accuracy and computational expediency. This will allow users to choose a level of sophistication appropriate for their application. Here, we describe the operation of the code and make comparisons with alternative radiative transfer codes of differing levels of complexity (SYN++, PYTHON and ARTIS). We then explore the consequence of adopting simple prescriptions for the calculation of atomic excitation, focusing on four species of relevance to Type Ia SN spectra-Si II, SII, MgII and Ca II. We also investigate the influence of three methods for treating line interactions on our synthetic spectra and the need for accurate radiative rate estimates in our scheme.

Analysis of voltage source converter-based high-voltage direct current under DC line-to-earth fault

DC line faults on high-voltage direct current (HVDC) systems utilising voltage source converters (VSCs) are a major issue for multi-terminal HVDC systems in which complete isolation of the faulted system is not a viable option. Of these faults, single line-to-earth faults are the most common fault scenario. To better understand the system under such faults, this study analyses the behaviour of HVDC systems based on both conventional two-level converter and multilevel modular converter technology, experiencing a permanent line-to-earth fault. Operation of the proposed system under two different earthing configurations of converter side AC transformer earthed with converter unearthed, and both converter and AC transformer unearthed, was analysed and simulated, with particular attention paid to the converter operation. It was observed that the development of potential earth loops within the system as a result of DC line-to-earth faults leads to substantial overcurrent and results in oscillations depending on the earthing configuration.

High-Speed Fully Homomorphic Encryption Over the Integers

A fully homomorphic encryption (FHE) scheme is envisioned as a key cryptographic tool in building a secure and reliable cloud computing environment, as it allows arbitrary evaluation of a ciphertext without revealing the plaintext. However, existing FHE implementations remain impractical due to very high time and resource costs. To the authors’ knowledge, this paper presents the first hardware implementation of a full encryption primitive for FHE over the integers using FPGA technology. A large-integer multiplier architecture utilising Integer-FFT multiplication is proposed, and a large-integer Barrett modular reduction module is designed incorporating the proposed multiplier. The encryption primitive used in the integer-based FHE scheme is designed employing the proposed multiplier and modular reduction modules. The designs are verified using the Xilinx Virtex-7 FPGA platform. Experimental results show that a speed improvement factor of up to 44 is achievable for the hardware implementation of the FHE encryption scheme when compared to its corresponding software implementation. Moreover, performance analysis shows further speed improvements of the integer-based FHE encryption primitives may still be possible, for example through further optimisations or by targeting an ASIC platform.

Synthesisable FFT cores

Methods are presented for developing synthesisable FFT cores. These are based on a modular approach in which parameterisable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organisation with generic commutator blocks to produce systems that offer 100% processor utilisation with storage requirements less than previous designs. The approach has been used to create generators for the automated synthesis of FFT cores that are portable across a broad range of silicon technologies. Resulting chip designs are competitive with manual methods but with significant reductions in design times.

Characterizing wear processes on orthopaedic materials using scanning probe microscopy

The operational lifetime of hip replacement prostheses can be severely limited due to the occurrence of excessive wear at the load-bearing interfaces. The aim of this study was to investigate how the surface topography of articulating counterfaces evolves over the duration of a laboratory wear run. It was observed that modular stainless steel femoral heads wearing against ultrahigh molecular weight polyethylene (UHMWPE) can themselves be subject to wearing. A comparison with retrieved in vivo-aged femoral heads shows many topographical similarities: in a qualitative sense, scratching and pitting are evident on laboratory and in vivo-worn femoral heads; quantitatively, roughness comparisons between the new and worn devices are seen to increase typically by a factor of 4 after laboratory wearing. The observations suggest that a particular wear mode, namely third-body wear, is responsible for the increased roughness. It is conjectured that third bodies might arise through surface fatigue wear on the metal counterface, Wear debris is also observed to have been generated from the polymer surface, creating rounded debris with sizes predominantly in the range 0.4-0.8 microns: dimensions that are comparable to values previously reported for in vivo generated debris.

Parker Morris and the economies of the Fordist house

The Parker Morris report of 1961 attempted, through the application of scientific principles, to define the minimum living space standards needed to accommodate household activities. But while early modernist research into ideas of existenzminimum were the work of avant-garde architects and thinkers, this report was commissioned by the British State. This normalization of scientific enquiry into space can be considered not only a response to new conditions in the mass production of housing – economies of scale, prefabrication, system-building and modular coordination – but also to the post-war boom in consumer goods. The domestic interior was assigned a key role as a privileged site of mass consumption as the production and micro-management of space in Britain became integral to the development of a planned national economy underpinned by Fordist principles. The apparently placeless and scale-less diagrams executed by Gordon Cullen to illustrate Parker Morris emblematize these relationships. Walls dissolve as space flows from inside to outside in a homogenized and ephemeral landscape whose limits are perhaps only the boundaries of the nation state and the circuits of capital.

Local operator multipliers and positivity

We establish an unbounded version of Stinespring's Theorem and a lifting result for Stinespring representations of completely positive modular maps defined on the space of all compact operators. We apply these results to study positivity for Schur multipliers. We characterise positive local Schur multipliers, and provide a description of positive local Schur multipliers of Toeplitz type. We introduce local operator multipliers as a non-commutative analogue of local Schur multipliers, and characterise them extending both the characterisation of operator multipliers from [16] and that of local Schur multipliers from [27]. We provide a description of the positive local operator multipliers in terms of approximation by elements of canonical positive cones.