From activity to active learning: drawing and dialogue interaction in virtual learning environments for computer-supported collaborative work in design.

Virtual learning environments (VLEs) would appear to be particular effective in computer-supported collaborative work (CSCW) for active learning. Most research studies looking at computer-supported collaborative design have focused on either synchronous or asynchronous modes of communication, but near-synchronous working has received relatively little attention. Yet it could be argued that near-synchronous communication encourages creative, rhetorical and critical exchanges of ideas, building on each other’s contributions. Furthermore, although many researchers have carried out studies on collaborative design protocol, argumentation and constructive interaction, little is known about the interaction between drawing and dialogue in near-synchronous collaborative design. The paper reports the first stage of an investigation into the requirements for the design and development of interactive systems to support the learning of collaborative design activities. The aim of the study is to understand the collaborative design processes while sketching in a shared white board and audio conferencing media. Empirical data on design processes have been obtained from observation of seven sessions with groups of design students solving an interior space-planning problem of a lounge-diner in a virtual learning environment, Lyceum, an in-house software developed by the Open University to support its students in collaborative learning.

Critical stages of the brewing process for changes in antioxidant activity and levels of phenolic compounds in ale

Samples were taken at each stage of brewing (malt, milling, mashing, wort separation, hop addition, boiling, whirlpool, dilution, fermentation, warm rest, chill-lagering, beer filtration, carbonation and bottling, pasteurization, and storage). The level of antioxidant activity of unfractionated, low-molecular-mass (LMM) and high-molecular-mass (HMM) fractions was measured by the 2,2'-azinobis(3-ethylbenzothiazoline-6-sulfortic acid) radical cation (ABTS(.+)) and ferric-reducing antioxidant power (FRAP) procedures. Polyphenol levels were assessed by HPLC. The LMM fraction (<5 kDa) was responsible for similar to80% of the level of antioxidant activity of the unfractionated malt and beer samples. In the unfractionated samples, significant decreases (P < 0.001) in antioxidant activity levels were observed after milling and beer filtration, with the decrease after beer filtration being accompanied by a significant decrease (P > 0.001) in catechin and ferulic acid levels. Increases in antioxidant activity levels were observed after mashing, boiling, fermentation, chill-lagering, and pasteurization, in line with previous studies on lager. Additionally, increases in the level of antioxidant activity occurred after wort separation and carbonation and bottling and were accompanied by increases in levels of most monitored polyphenols. Data from the ABTS(.-) and FRAP assays indicated that the compounds contributing to the levels of antioxidant activity responded differently in the two procedures. Levels of ferulic, vanillic, and chlorogenic acids and catechin accounted for 45-61% of the variation in antioxidant activity levels.

Structure oil-absorption relationships during deep-fat frying

Analysis of the oil-absorption process in deep-fat fried potato cylinders (frying temperatures of 155degreesC, 170degreesC, and 185degreesC) allowed to distinguish 3 oil fractions: structural oil (absorbed during frying), penetrated surface oil (suctioned during cooling), and surface oil. Results showed that a small amount of oil penetrates during frying because most of the oil was picked up at the end of the process, suggesting that oil uptake and water removal are not synchronous phenomena. After cooling, oil was located either on the surface of the chip or suctioned into the porous crust microstructure, with an inverse relationship between them for increasing frying times.

Pullpipelining: A technique for systolic pipelined circuits

Pullpipelining, a pipeline technique where data is pulled from successor stages from predecessor stages is proposed Control circuits using a synchronous, a semi-synchronous and an asynchronous approach are given. Simulation examples for a DLX generic RISC datapath show that common control pipeline circuit overhead is avoided using the proposal. Applications to linear systolic arrays in cases when computation is finished at early stages in the array are foreseen. This would allow run-time data-driven digital frequency modulation of synchronous pipelined designs. This has applications to implement algorithms exhibiting average-case processing time using a synchronous approach.

Building collaborative environments for advanced computing

Synchronous collaborative systems allow geographically distributed users to form a virtual work environment enabling cooperation between peers and enriching the human interaction. The technology facilitating this interaction has been studied for several years and various solutions can be found at present. In this paper, we discuss our experiences with one such widely adopted technology, namely the Access Grid [1]. We describe our experiences with using this technology, identify key problem areas and propose our solution to tackle these issues appropriately. Moreover, we propose the integration of Access Grid with an Application Sharing tool, developed by the authors. Our approach allows these integrated tools to utilise the enhanced features provided by our underlying dynamic transport layer.

An asynchronous distributed dynamic channel assignment scheme for dense WLANs

Wireless local area networks (WLANs) have changed the way many of us communicate, work, play and live. Due to its popularity, dense deployments are becoming a norm in many cities around the world. However, increased interference and traffic demands can severely limit the aggregate throughput achievable if an effective channel assignment scheme is not used. In this paper, we propose an enhanced asynchronous distributed and dynamic channel assignment scheme that is simple to implement, does not require any knowledge of the throughput function, allows asynchronous channel switching by each access point (AP) and is superior in performance. Simulation results show that our proposed scheme converges much faster than previously reported synchronous schemes, with a reduction in convergence time and channel switches by tip to 73.8% and 30.0% respectively.

A clocking technique for FPGA pipelined designs

This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits. (C) 2004 Elsevier B.V. All rights reserved.

Collaborative virtual environment for advanced computing

Synchronous collaborative systems allow geographically distributed participants to form a virtual work environment enabling cooperation between peers and enriching the human interaction. The technology facilitating this interaction has been studied for several years and various solutions can be found at present. In this paper, we discuss our experiences with one such widely adopted technology, namely the Access Grid. We describe our experiences with using this technology, identify key problem areas and propose our solution to tackle these issues appropriately. Moreover, we propose the integration of Access Grid with an Application Sharing tool, developed by the authors. Our approach allows these integrated tools to utilise the enhanced features provided by our underlying dynamic transport layer.

Blind adaptive channel estimation for dual-rate DS/CDMA signals

This letter proposes the subspace-based blind adaptive channel estimation algorithm for dual-rate quasi-synchronous DS/CDMA systems, which can operate at the low-rate (LR) or high-rate (HR) mode. Simulation results show that the proposed blind adaptive algorithm at the LR mode has a better performance than that at the HR mode, with the cost of an increasing computational complexity.

Synchronisation error resistant multiuser detection for asynchronous CDMA

Linear CDMA detectors have emerged as a promising solution to multiple access interference (MAI) suppression. Unfortunately, most existing linear detectors suffer from high sensitivity to synchronisation errors (also termed parameter estimation error), and synchronisation error resistant detectors have so far not been as widely investigated as they should have. This paper extends the minimum variance distortionless response (MVDR) detector, proposed previously by this author (Zheng 2000) for synchronous systems, to asynchronous systems. It has been shown that the MVDR structure is equally effective for asynchronous systems, especially for the weaker users.

Subspace-based blind adaptive multiuser detection for multirate DS/CDMA signals

The existing dual-rate blind linear detectors, which operate at either the low-rate (LR) or the high-rate (HR) mode, are not strictly blind at the HR mode and lack theoretical analysis. This paper proposes the subspace-based LR and HR blind linear detectors, i.e., bad decorrelating detectors (BDD) and blind MMSE detectors (BMMSED), for synchronous DS/CDMA systems. To detect an LR data bit at the HR mode, an effective weighting strategy is proposed. The theoretical analyses on the performance of the proposed detectors are carried out. It has been proved that the bit-error-rate of the LR-BDD is superior to that of the HR-BDD and the near-far resistance of the LR blind linear detectors outperforms that of its HR counterparts. The extension to asynchronous systems is also described. Simulation results show that the adaptive dual-rate BMMSED outperform the corresponding non-blind dual-rate decorrelators proposed by Saquib, Yates and Mandayam (see Wireless Personal Communications, vol. 9, p.197-216, 1998).

Identification and minimization of IIR tap coefficients for the cancellation of complex multipath in terrestrial television

By using a deterministic approach, an exact form for the synchronous detected video signal under a ghosted condition is presented. Information regarding the phase quadrature-induced ghost component derived from the quadrature forming nature of the vestigial sideband (VSB) filter is obtained by crosscorrelating the detected video with the ghost cancel reference (GCR) signal. As a result, the minimum number of taps required to correctly remove all the ghost components is subsequently presented. The results are applied to both National Television System Committee (NTSC) and phase alternate line (PAL) television.

The concept of a new video detector for ghosted IF signals

The effect of terrestrial television multipath signals on the intermediate frequency (IF) vestigial sideband filter and the video detector are discussed. A new detector is proposed which, by processing the detected phase quadrature information, derives the correct phase for synchronous detection in the presence of multipath effects. This minimizes dispersion and produces a detected video signal with the linear addition of any ghosts.

Improving mW/MHz ratio in FPGAs pipelined designs

This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and practical systolic design as an example. The technique in essence is a simple replacement of the clocking mechanism for the pipe-storage elements; however no extra design effort is needed. The results show that the proposed technique allows immediate power and area-time savings of existing designs rather than exploring potential benefits by a new logic design to the problem using the classic pipeline clocking mechanism.

Pipelining considerations for an FPGA case

This paper presents a semi-synchronous pipeline scheme, here referred as single-pulse pipeline, to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). Area and timing considerations are given for a general case and later applied to a systolic circuit as illustration. The single-pulse pipeline can manage asynchronous worst-case data completion and it is evaluated against two chosen asynchronous pipelining: a four-phase bundle-data pipeline and a doubly-latched asynchronous pipeline. The semi-synchronous pipeline proposal takes less FPGA area and operates faster than the two selected fully-asynchronous schemes for an FPGA case.