Analysis methods for meso- and macroporous silicon etching baths

Analysis methods for electrochemical etching baths consisting of various concentrations of hydrofluoric acid (HF) and an additional organic surface wetting agent are presented. These electrolytes are used for the formation of meso- and macroporous silicon. Monitoring the etching bath composition requires at least one method each for the determination of the HF concentration and the organic content of the bath. However, it is a precondition that the analysis equipment withstands the aggressive HF. Titration and a fluoride ion-selective electrode are used for the determination of the HF and a cuvette test method for the analysis of the organic content, respectively. The most suitable analysis method is identified depending on the components in the electrolyte with the focus on capability of resistance against the aggressive HF.

Contactless Spectral-Dependent Measurement of Bulk Lifetime and Surface Recombination Velocity in Silicon Photovoltaic Materials

Charge carrier lifetime measurements in bulk or unfinished photovoltaic (PV) materials allow for a more accurate estimate of power conversion efficiency in completed solar cells. In this work, carrier lifetimes in PV- grade silicon wafers are obtained by way of quasi-steady state photoconductance measurements. These measurements use a contactless RF system coupled with varying narrow spectrum input LEDs, ranging in wavelength from 460 nm to 1030 nm. Spectral dependent lifetime measurements allow for determination of bulk and surface properties of the material, including the intrinsic bulk lifetime and the surface recombination velocity. The effective lifetimes are fit to an analytical physics-based model to determine the desired parameters. Passivated and non-passivated samples are both studied and are shown to have good agreement with the theoretical model.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Deposition of Intrinsic a-Si:H by ECR-CVD to Passivate the Crystalline Silicon Heterointerface in HIT Solar Cells

We have deposited intrinsic amorphous silicon (a-Si:H) using the electron cyclotron resonance (ECR) chemical vapor deposition technique in order to analyze the a-Si:H/c-Si heterointerface and assess the possible application in heterojunction with intrinsic thin layer (HIT) solar cells. Physical characterization of the deposited films shows that the hydrogen content is in the 15-30% range, depending on deposition temperature. The optical bandgap value is always comprised within the range 1.9- 2.2 eV. Minority carrier lifetime measurements performed on the heterostructures reach high values up to 1.3 ms, indicating a well-passivated a-Si:H/c-Si heterointerface for deposition temperatures as low as 100°C. In addition, we prove that the metal-oxide- semiconductor conductance method to obtain interface trap distribution can be applied to the a-Si:H/c-Si heterointerface, since the intrinsic a-Si:H layer behaves as an insulator at low or negative bias. Values for the minimum of D_it as low as 8 × 10^10 cm^2 · eV^-1 were obtained for our samples, pointing to good surface passivation properties of ECR-deposited a-Si:H for HIT solar cell applications.

Limitations of high pressure sputtering for amorphous silicon deposition

Amorphous silicon thin films were deposited using the high pressure sputtering (HPS) technique to study the influence of deposition parameters on film composition, presence of impurities, atomic bonding characteristics and optical properties. An optical emission spectroscopy (OES) system has been used to identify the different species present in the plasma in order to obtain appropriate conditions to deposit high purity films. Composition measurements in agreement with the OES information showed impurities which critically depend on the deposition rate and on the gas pressure. We prove that films deposited at the highest RF power and 3.4 × 10^−2 mbar, exhibit properties as good as the ones of the films deposited by other more standard techniques.

L1 track finding for a time multiplexed trigger

At the HL-LHC, proton bunches will cross each other every 25. ns, producing an average of 140 pp-collisions per bunch crossing. To operate in such an environment, the CMS experiment will need a L1 hardware trigger able to identify interesting events within a latency of 12.5. μs. The future L1 trigger will make use also of data coming from the silicon tracker to control the trigger rate. The architecture that will be used in future to process tracker data is still under discussion. One interesting proposal makes use of the Time Multiplexed Trigger concept, already implemented in the CMS calorimeter trigger for the Phase I trigger upgrade. The proposed track finding algorithm is based on the Hough Transform method. The algorithm has been tested using simulated pp-collision data. Results show a very good tracking efficiency. The algorithm will be demonstrated in hardware in the coming months using the MP7, which is a μTCA board with a powerful FPGA capable of handling data rates approaching 1. Tb/s.

Simultaneous determination of carotenoids and tocochromanols from palm hybrid oil by hplc with photodiode array and fluorescence detectors.

2016

Electrical characterization of CVD diamond-n(+) silicon junctions

The electrical characteristics of CVD-diamond/n(+)-Si heterojunction devices are reported. Below 250 K the diodes show an unusual inversion of their rectification properties. This behavior is attributed to an enhanced tunneling component due to interface states, which change their occupation with the applied bias. The temperature dependence of the loss tangent shows two relaxation processes with different activation energies. These processes are likely related with two parallel charge transport mechanisms, one through the diamond grain, and the other through the grain boundary. (C) 2001 Elsevier Science B.V. Ah rights reserved.

Electrical characterization of pn-junctions of PPV and silicon

Poly(phenylene vinylene) (PPV) grown via the precursor route, deposited on top of heavily doped n-type silicon, was studied using electrical measurement techniques. The results are compared to PPV grown via deposition of soluble derivative (MEH-PPV). The two types are very similar. They have comparable free carrier densities and both show minority-carrier effects. The activation energy found via the loss tangent is 0.13 eV. The effect of exposure to oxygen is visible in the capacitance and the current.

CO-ELECTROPHORETIC DEPOSITION OF LIQUID METAL AND SILICON FOR LITHIUM-ION BATTERY APPLICATION

A low cost electrophoretic deposition (EPD) process was successfully used for liquid metal thin film deposition with a high depositing rate of 0.6 µ/min. Furthermore, silicon nano-powder and liquid metal were then simultaneously deposited as the negative electrode of lithium-ion battery by a technology called co-EPD. The liquid metal was hoping to act as the matrix for silicon particles during lithium ion insertion and distraction. Half-cell testing was performed using as prepared co-EPD sample. An initial discharge capacity of 1500 mAh/g was reported for nano-silicon and galinstan electrode, although the capacity fading issue of these samples was also observed.

THE EFFECT OF ANNEALING ON AMORPHOUS SILICON BASED SOLAR PHOTOVOLTAIC THERMAL SYSTEM (PV/T) AND APPROPRIATE GLOBAL DISPATCH STRATEGIES

Previous work has shown that high-temperature short-term spike thermal annealing of hydrogenated amorphous silicon (a-Si:H) photovoltaic thermal (PVT) systems results in higher electrical energy output. The relationship between temperature and performance of a-Si:H PVT is not simple as high temperatures during thermal annealing improves the immediate electrical performance following an anneal, but during the anneal it creates a marked drop in electrical performance. In addition, the power generation of a-Si:H PVT depends on both the environmental conditions and the Staebler-Wronski Effect kinetics. In order to improve the performance of a-Si:H PVT systems further, this paper reports on the effect of various dispatch strategies on system electrical performance. Utilizing experimental results from thermal annealing, an annealing model simulation for a-Si:Hbased PVT was developed and applied to different cities in the U.S. to investigate potential geographic effects on the dispatch optimization of the overall electrical PVT systems performance and annual electrical yield. The results showed that spike thermal annealing once per day maximized the improved electrical energy generation. In the outdoor operating condition this ideal behavior deteriorates and optimization rules are required to be implemented.

Silicon Photonic Device for Wavelength Sensing and Monitoring

Over the last decade advances and innovations from Silicon Photonics technology were observed in the telecommunications and computing industries. This technology which employs Silicon as an optical medium, relies on current CMOS micro-electronics fabrication processes to enable medium scale integration of many nano-photonic devices to produce photonic integrated circuitry. However, other fields of research such as optical sensor processing can benefit from silicon photonics technology, specially in sensors where the physical measurement is wavelength encoded. In this research work, we present a design and application of a thermally tuned silicon photonic device as an optical sensor interrogator. The main device is a micro-ring resonator filter of 10 $\mu m$ of diameter. A photonic design toolkit was developed based on open source software from the research community. With those tools it was possible to estimate the resonance and spectral characteristics of the filter. From the obtained design parameters, a 7.8 x 3.8 mm optical chip was fabricated using standard micro-photonics techniques. In order to tune a ring resonance, Nichrome micro-heaters were fabricated on top of the device. Some fabricated devices were systematically characterized and their tuning response were determined. From measurements, a ring resonator with a free-spectral-range of 18.4 nm and with a bandwidth of 0.14 nm was obtained. Using just 5 mA it was possible to tune the device resonance up to 3 nm. In order to apply our device as a sensor interrogator in this research, a model of wavelength estimation using time interval between peaks measurement technique was developed and simulations were carried out to assess its performance. To test the technique, an experiment using a Fiber Bragg grating optical sensor was set, and estimations of the wavelength shift of this sensor due to axial strains yield an error within 22 pm compared to measurements from spectrum analyzer. Results from this study implies that signals from FBG sensors can be processed with good accuracy using a micro-ring device with the advantage of ts compact size, scalability and versatility. Additionally, the system also has additional applications such as processing optical wavelength shifts from integrated photonic sensors and to be able to track resonances from laser sources.

Improved Electronics for the Hall A Detectors at JLab: Summing Modules and VDC Amplifier/Discriminator Cards

Testing of summing electronics and VDC A/D Cards was performed to assure proper functioning and operation within defined parameters. In both the summing modules and the VDC A/D cards, testing for minimum threshold voltage for each channel and crosstalk between neighboring channels was performed. Additionally, the modules were installed in Hall A with input signals from shower detectors arranged to establish a trigger by summing signals together with the use of tested modules. Testing involved utilizing a pulser to mimic PMT signals, a discriminator, an attenuator, a scaler, a level translator, an oscilloscope, a high voltage power supply, and a special apparatus used to power and send signal to the A/D cards. After testing, modules were obtained that meet necessary criteria for use in the APEX experiment, and the A/D cards obtained were determined to have adequate specifications for their utilization, with specific results included in the appendix.

A comparative analysis of the characterization methods for submicron silicon waveguide propagation loss

An important parameter in integrated optical device is the propagation loss of the waveguide. Its characterization gives the information of the fabrication quality as well as the information of other passive devices on the chip as it is the basic building block of the passive devices. Although, over the last three decades many methods have been developed, there is not a single standard present yet. This paper presents a comparative analysis of the methods existing from the past as well as methods developed very recently in order to provide a complete picture of the pros and cons of different types of methods and from this comparison the best method is suggested according to the authors opinion. To support the claim, apart from the analytical comparison, this paper also presents a comparison performed with the experimental results between the suggested best method which is recently proposed by Massachusetts Institute of Technology (MIT) researchers based on undercoupled all-pass microring structure and the popular cut-back method.