Implementation of Discrete and Integrated IT: The Role of Organisational Structure and Culture

ntegrated organisational IT systems, such as enterprise resource planning (ERP), supply chain management (SCM) and digital manufacturing (DM), have promised and delivered substantial performance benefits to many adopting firms. However, implementations of such systems have tended to be problematic. ERP projects, in particular, are prone to cost and time overruns, not delivering anticipated benefits and often being abandoned before completion. While research has developed around IT implementation, this has focused mainly on standalone (or discrete), as opposed to integrated, IT systems. Within this literature, organisational (i.e., structural and cultural) characteristics have been found to influence implementation success. The key aims of this research are (a) to investigate the role of organisational characteristics in determining IT implementation success; (b) to determine whether their influence differs for integrated IT and discrete IT projects; and (c) to develop specific guidelines for managers of integrated IT implementations. An in-depth comparative case study of two IT projects was conducted within a major aerospace manufacturing company.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

Exploring the adoption and implementation of discrete and integrated IT systems: A Framework for analysis

Despite the substantial organisational benefits of integrated IT, the implementation of such systems – and particularly Enterprise Resource Planning (ERP) systems – has tended to be problematic, stimulating an extensive body of research into ERP implementation. This research has remained largely separate from the main IT implementation literature. At the same time, studies of IT implementation have generally adopted either a factor or process approach; both have major limitations. To address these imitations, factor and process perspectives are combined here in a unique model of IT implementation. We argue that • the organisational factors which determine successful implementation differ for integrated and traditional, discrete IT • failure to manage these differences is a major source of integrated IT failure. The factor/process model is used as a framework for proposing differences between discrete and integrated IT.

FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition

A scalable large vocabulary, speaker independent speech recognition system is being developed using Hidden Markov Models (HMMs) for acoustic modeling and a Weighted Finite State Transducer (WFST) to compile sentence, word, and phoneme models. The system comprises a software backend search and an FPGA-based Gaussian calculation which are covered here. In this paper, we present an efficient pipelined design implemented both as an embedded peripheral and as a scalable, parallel hardware accelerator. Both architectures have been implemented on an Alpha Data XRC-5T1, reconfigurable computer housing a Virtex 5 SX95T FPGA. The core has been tested and is capable of calculating a full set of Gaussian results from 3825 acoustic models in 9.03 ms which coupled with a backend search of 5000 words has provided an accuracy of over 80%. Parallel implementations have been designed with up to 32 cores and have been successfully implemented with a clock frequency of 133?MHz.

Comparing the implementation of two-dimensional numerical quadrature on GPU, FPGA and ClearSpeed systems to study electron scattering by atoms

The use of accelerators, with compute architectures different and distinct from the CPU, has become a new research frontier in high-performance computing over the past ?ve years. This paper is a case study on how the instruction-level parallelism offered by three accelerator technologies, FPGA, GPU and ClearSpeed, can be exploited in atomic physics. The algorithm studied is the evaluation of two electron integrals, using direct numerical quadrature, a task that arises in the study of intermediate energy electron scattering by hydrogen atoms. The results of our ‘productivity’ study show that while each accelerator is viable, there are considerable differences in the implementation strategies that must be followed on each.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.