Different rooms, different voices: double-breasting, multi-channel representation and the managerial agenda

Double-breasting has been identified as where companies run union voice and non-union voice mechanisms across different plants. While research has focused on the incidence of such arrangements, there is a dearth of evidence into the dynamics of it. This article seeks to complement existing research by examining the contours of double-breasting in a case study organisation. The findings suggest that more research is necessary into the dynamics of double-breasting in terms of how voice in sites affects each other and the extent to which running different regimes affects the managerial agenda.

Non-union employee representation, union avoidance and the managerial agenda

Non-union employee representation is an area which has attracted much interest in the voice literature. Much of the literature has been shaped by a dialogue which considers NERs as a means of union avoidance. More recently however scholars have suggested that for NERs to work in such contexts, they may need to be imbued with a higher set of functionalities to remain viable entities. Using a critical case study of a union recognition drive and managerial response in the form of an NER, this article contributes to a more nuanced interpretation of the literature dialogue than hitherto exists. A core component of the findings directly challenge existing interpretations within the field; namely that NERs are shaped by a paradox of managerial action. It is argued that the NER failed to satisfy for employees because of a structural remit, rather than through any paradox in managerial intent.

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.