955 resultados para VLSI CAD


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BACKGROUND: Cardiovascular disease (CVD) represents a leading cause of mortality worldwide, especially in the elderly. Lowering the number of CVD deaths requires preventive strategies targeted on the elderly.

OBJECTIVE: The objective was to generate evidence on the association between WHO dietary recommendations and mortality from CVD, coronary artery disease (CAD), and stroke in the elderly aged ≥60 y.

DESIGN: We analyzed data from 10 prospective cohort studies from Europe and the United States comprising a total sample of 281,874 men and women free from chronic diseases at baseline. Components of the Healthy Diet Indicator (HDI) included saturated fatty acids, polyunsaturated fatty acids, mono- and disaccharides, protein, cholesterol, dietary fiber, and fruit and vegetables. Cohort-specific HRs adjusted for sex, education, smoking, physical activity, and energy and alcohol intakes were pooled by using a random-effects model.

RESULTS: During 3,322,768 person-years of follow-up, 12,492 people died of CVD. An increase of 10 HDI points (complete adherence to an additional WHO guideline) was, on average, not associated with CVD mortality (HR: 0.94; 95% CI: 0.86, 1.03), CAD mortality (HR: 0.99; 95% CI: 0.85, 1.14), or stroke mortality (HR: 0.95; 95% CI: 0.88, 1.03). However, after stratification of the data by geographic region, adherence to the HDI was associated with reduced CVD mortality in the southern European cohorts (HR: 0.87; 95% CI: 0.79, 0.96; I(2) = 0%) and in the US cohort (HR: 0.85; 95% CI: 0.83, 0.87; I(2) = not applicable).

CONCLUSION: Overall, greater adherence to the WHO dietary guidelines was not significantly associated with CVD mortality, but the results varied across regions. Clear inverse associations were observed in elderly populations in southern Europe and the United States.

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Background: The nature and underlying mechanisms of an inverse association between adult height and the risk of coronary artery disease (CAD) are unclear. 
Methods: We used a genetic approach to investigate the association between height and CAD, using 180 height-associated genetic variants. We tested the association between a change in genetically determined height of 1 SD (6.5 cm) with the risk of CAD in 65,066 cases and 128,383 controls. Using individual-level genotype data from 18,249 persons, we also examined the risk of CAD associated with the presence of various numbers of height-associated alleles. To identify putative mechanisms, we analyzed whether genetically determined height was associated with known cardiovascular risk factors and performed a pathway analysis of the height-associated genes. 
Results: We observed a relative increase of 13.5% (95% confidence interval [CI], 5.4 to 22.1; P<0.001) in the risk of CAD per 1-SD decrease in genetically determined height. There was a graded relationship between the presence of an increased number of height-raising variants and a reduced risk of CAD (odds ratio for height quartile 4 versus quartile 1, 0.74; 95% CI, 0.68 to 0.84; P<0.001). Of the 12 risk factors that we studied, we observed significant associations only with levels of low-density lipoprotein cholesterol and triglycerides (accounting for approximately 30% of the association). We identified several overlapping pathways involving genes associated with both development and atherosclerosis. 
Conclusions: There is a primary association between a genetically determined shorter height and an increased risk of CAD, a link that is partly explained by the association between shorter height and an adverse lipid profile. Shared biologic processes that determine achieved height and the development of atherosclerosis may explain some of the association. (Funded by the British Heart Foundation and others.)

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Virtual topology operations have been utilized to generate an analysis topology definition suitable for downstream mesh generation. Detailed descriptions are provided for virtual topology merge and split operations for all topological entities, where virtual decompositions are robustly linked to the underlying geometry. Current virtual topology technology is extended to allow the virtual partitioning of volume cells. A valid description of the topology, including relative orientations, is maintained which enables downstream interrogations to be performed on the analysis topology description, such as determining if a specific meshing strategy can be applied to the virtual volume cells. As the virtual representation is a true non-manifold description of the sub-divided domain the interfaces between cells are recorded automatically. Therefore, the advantages of non-manifold modelling are exploited within the manifold modelling environment of a major commercial CAD system without any adaptation of the underlying CAD model. A hierarchical virtual structure is maintained where virtual entities are merged or partitioned. This has a major benefit over existing solutions as the virtual dependencies here are stored in an open and accessible manner, providing the analyst with the freedom to create, modify and edit the analysis topology in any preferred sequence.

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Field programmable gate array devices boast abundant resources with which custom accelerator components for signal, image and data processing may be realised; however, realising high performance, low cost accelerators currently demands manual register transfer level design. Software-programmable ’soft’ processors have been proposed as a way to reduce this design burden but they are unable to support performance and cost comparable to custom circuits. This paper proposes a new soft processing approach for FPGA which promises to overcome this barrier. A high performance, fine-grained streaming processor, known as a Streaming Accelerator Element, is proposed which realises accelerators as large scale custom multicore networks. By adopting a streaming execution approach with advanced program control and memory addressing capabilities, typical program inefficiencies can be almost completely eliminated to enable performance and cost which are unprecedented amongst software-programmable solutions. When used to realise accelerators for fast fourier transform, motion estimation, matrix multiplication and sobel edge detection it is shown how the proposed architecture enables real-time performance and with performance and cost comparable with hand-crafted custom circuit accelerators and up to two orders of magnitude beyond existing soft processors.

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Wearable devices performing advanced bio-signal analysis algorithms are aimed to foster a revolution in healthcare provision of chronic cardiac diseases. In this context, energy efficiency is of paramount importance, as long-term monitoring must be ensured while relying on a tiny power source. Operating at a scaled supply voltage, just above the threshold voltage, effectively helps in saving substantial energy, but it makes circuits, and especially memories, more prone to errors, threatening the correct execution of algorithms. The use of error detection and correction codes may help to protect the entire memory content, however it incurs in large area and energy overheads which may not be compatible with the tight energy budgets of wearable systems. To cope with this challenge, in this paper we propose to limit the overhead of traditional schemes by selectively detecting and correcting errors only in data highly impacting the end-to-end quality of service of ultra-low power wearable electrocardiogram (ECG) devices. This partition adopts the protection of either significant words or significant bits of each data element, according to the application characteristics (statistical properties of the data in the application buffers), and its impact in determining the output. The proposed heterogeneous error protection scheme in real ECG signals allows substantial energy savings (11% in wearable devices) compared to state-of-the-art approaches, like ECC, in which the whole memory is protected against errors. At the same time, it also results in negligible output quality degradation in the evaluated power spectrum analysis application of ECG signals.

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This paper describes a novel RISC microprocessor that can be utilised to rapidly develop a reprogrammable and high performance embedded security-processing system in SoC designs. Generic and innovative algorithm-specific instructions have been developed for a wide range of private-key and hash algorithms. To the authors' knowledge, this is the first generic cryptographic microprocessor to be reported in the literature.

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Os estudos de maquinabilidade de biomateriais e outros materiais aplicados na área médica são extensos. Todavia, muitos destes estudos recorrem a modelos de geometria regular e operações elementares de maquinagem. Relativamente a estas, os estudos académicos atualmente disponíveis mostram que a tecnologia preferencial é o torneamento, opção que se fundamenta na simplicidade de análise (corte ortogonal). Saliente-se ainda que, neste contexto, a liga de titânio Ti-6Al-4V constitui o biomaterial mais utilizado. Numa perspetiva complementar, refira-se que as publicações científicas evidenciam que a informação disponível sobre a fresagem Ti-6Al-4V não é muito extensa e a do Co-28Cr-6Mo é quase inexistente. A presente dissertação enquadra-se neste domínio e representa mais uma contribuição para o estudo da maquinabilidade das ligas de Titânio e de crómio-cobalto. A aplicação de operações de maquinagem complexas, através do recurso a programas informáticos de fabrico assistido por computador (CAM), em geometrias complexas, como é o caso das próteses femorais anatómicas, e o estudo comparativo da maquinabilidade das ligas Co-28Cr-6Mo e Ti-6Al-4V, constituem os objetivos fundamentais deste trabalho de doutoramento. Neste trabalho aborda-se a problemática da maquinabilidade das ligas metálicas usadas nos implantes ortopédicos, nomeadamente as ligas de titânio, de crómiocobalto e os aços Inoxidáveis. Efetua-se ainda um estudo da maquinagem de uma prótese femoral com uma forma geométrica complexa, onde as operações de corte foram geradas recorrendo às tecnologias de fabrico assistido por computador (CAD/CAM). Posteriormente, procedeu-se ao estudo da maquinabilidade das duas ligas usadas neste trabalho, dando uma atenção particular à determinação das forças de corte para diferentes velocidades de corte. Para além da monitorização da evolução da força de corte, o desgaste das ferramentas, a dureza e a rugosidade foram avaliadas, em função da velocidade de corte imposta. Por fim, com base nas estratégias de maquinagem adotadas, analisa-se a maquinabilidade e selecionam-se os parâmetros de corte mais favoráveis para as ligas de Titânio e Crómio-cobalto. Os resultados obtidos mostram que a liga de crómio-cobalto induz maior valor de força de corte do que a liga de titânio. Observa-se um aumento progressivo das forças de corte quando a velocidade de corte aumenta, até atingir o valor máximo para a velocidade de corte de 80m/min, após a qual, a força de corte tende a diminuir. Apesar do fabricante das ferramentas recomendar a velocidade de corte de 50 m/min para ambos os materiais, conclui-se que a velocidade de corte de 65 m/min induz o mesmo desgaste na ferramenta de corte no caso da liga de titânio, e menor desgaste no caso da liga de crómio-cobalto.

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O que é a animação? O que é o cinema? Qual é a relação entre ambos? Este livro busca responder a essas perguntas e ao mesmo tempo construir uma estrutura concetual para a interpretação do filme animado.

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In this paper, the performance and convergence time comparisons of various low-complexity LMS algorithms used for the coefficient update of adaptive I/Q corrector for quadrature receivers are presented. We choose the optimum LMS algorithm suitable for low complexity, high performance and high order QAM and PSK constellations. What is more, influence of the finite bit precision on VLSI implementation of such algorithms is explored through extensive simulations and optimum wordlengths established.

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Introdução: A correta avaliação das capacidades do idoso será fundamental na diminuição do risco de queda inerente ao envelhecimento. Os Smartphones são uma boa ferramenta para a avaliação das capacidades em idosos. Objetivo: Verificar se o smartphone é uma ferramenta de avaliação do ângulo de dorsiflexão ativa da tibiotársica (Dors. TT) e em diferentes parâmetros relacionados com a marcha. ; Métodos: Estudo transversal correlacional, com amostra composta por 27 indivíduos com mais de 60 anos. Procedeu-se à recolha de dados através de um sistema de análise cinemática em 3D com conexão a uma plataforma de forças e de uma aplicação para Smartphone (Fraunhofer®, Porto, Portugal), de forma a verificar a funcionalidade desta última. As variáveis medidas foram a Dors. TT; e todas a variáveis relacionadas com a marcha. Resultados: A dors. TT apresentou uma correlação forte positiva (rs=0,8; p<0,001) entre os dados dos dois instrumentos, assim como no balanço pélvico (rp=0,8; p<0,001), na velocidade na marcha (rp=0,7; p<0,001) e no nº de passos posteriores (rs=0,8; p<0,001). Observou-se uma correlação moderada positiva na duração do passo direito, na duração do passo, na duração da passada, na cadência, no comprimento do passo esq., no comprimento do passo e no deslocamento lateral da pélvis (rp=0,6; p≤0.008). Na percentagem da fase de apoio (%FA) (rs =-0.6; p= 0.007) e na medição da cadência lateral (rs =-0.4; p= 0.042) observou-se uma correlação moderada negativa e na cad. post. (rs=-0,7; p<0,001) uma correlação forte negativa. Conclusão: A aplicação para Smartphone parece ser uma ferramenta útil para avaliar corretamente o ângulo de dorsiflexão da tibiotársica, a contagem do número de passos no sentido posterior, o balanço pélvico e a velocidade. Contudo, necessita ser reajustada para as outras variáveis.

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Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Automação e Electrónica Industrial

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Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

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The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.

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This Thesis has the main target to make a research about FPAA/dpASPs devices and technologies applied to control systems. These devices provide easy way to emulate analog circuits that can be reconfigurable by programming tools from manufactures and in case of dpASPs are able to be dynamically reconfigurable on the fly. It is described different kinds of technologies commercially available and also academic projects from researcher groups. These technologies are very recent and are in ramp up development to achieve a level of flexibility and integration to penetrate more easily the market. As occurs with CPLD/FPGAs, the FPAA/dpASPs technologies have the target to increase the productivity, reducing the development time and make easier future hardware reconfigurations reducing the costs. FPAA/dpAsps still have some limitations comparing with the classic analog circuits due to lower working frequencies and emulation of complex circuits that require more components inside the integrated circuit. However, they have great advantages in sensor signal condition, filter circuits and control systems. This thesis focuses practical implementations of these technologies to control system PID controllers. The result of the experiments confirms the efficacy of FPAA/dpASPs on signal condition and control systems.

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Dissertação para obtenção do Grau de Mestre em Engenharia Eletrotécnica e Computadores