983 resultados para Program computer


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Background:Cardiovascular diseases affect people worldwide. Individuals with Down Syndrome (DS) have an up to sixteen-time greater risk of mortality from cardiovascular diseases.Objective:To evaluate the effects of aerobic and resistance exercises on blood pressure and hemodynamic variables of young individuals with DS.Methods:A total of 29 young individuals with DS participated in the study. They were divided into two groups: aerobic training (AT) (n = 14), and resistance training (TR) (n = 15). Their mean age was 15.7 ± 2.82 years. The training program lasted 12 weeks, and had a frequency of three times a week for AT and twice a week for RT. AT was performed in treadmill/ bicycle ergometer, at an intensity between 50%-70% of the HR reserve. RT comprised nine exercises with three sets of 12 repetition-maximum. Systolic blood pressure (SBP), diastolic blood pressure (DBP), mean blood pressure (MBP) and hemodynamic variables were assessed beat-to-beat using the Finometer device before/after the training program. Descriptive analysis, the Shapiro-Wilk test to check the normality of data, and the two-way ANOVA for repeated measures were used to compare pre- and post-training variables. The Pearson’s correlation coefficient was calculated to correlate hemodynamic variables. The SPSS version 18.0 was used with the significance level set at p < 0.05.Results:After twelve weeks of aerobic and/or resistance training, significant reductions in variables SBP, DBP and MBP were observed.Conclusion:This study suggests a chronic hypotensive effect of moderate aerobic and resistance exercises on young individuals with DS.

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Magdeburg, Univ., Fak. für Informatik, Diss., 2009

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Magdeburg, Univ., Fak. für Informatik, Diss., 2012

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An appropriate assessment of end-to-end network performance presumes highly efficient time tracking and measurement with precise time control of the stopping and resuming of program operation. In this paper, a novel approach to solving the problems of highly efficient and precise time measurements on PC-platforms and on ARM-architectures is proposed. A new unified High Performance Timer and a corresponding software library offer a unified interface to the known time counters and automatically identify the fastest and most reliable time source, available in the user space of a computing system. The research is focused on developing an approach of unified time acquisition from the PC hardware and accordingly substituting the common way of getting the time value through Linux system calls. The presented approach provides a much faster means of obtaining the time values with a nanosecond precision than by using conventional means. Moreover, it is capable of handling the sequential time value, precise sleep functions and process resuming. This ability means the reduction of wasting computer resources during the execution of a sleeping process from 100% (busy-wait) to 1-1.5%, whereas the benefits of very accurate process resuming times on long waits are maintained.

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Magdeburg, Univ., Fak. für Informatik, Diss., 2013

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Magdeburg, Univ., Fak. für Informatik, Diss., 2014

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The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.

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Magdeburg, Univ., Fak. für Naturwiss., Diss., 2015

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Scientific Framework