Compact three-dimensional silicon termination solutions for high voltage SOI SuperJunction

This paper demonstrates and discusses novel "three dimensional" silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures. The proposed designs are both compact and effective in safely distributing the electrostatic potential away from the active device area. The designs are based on the utilization of existing layers in the device fabrication line, hence resulting in no extra complexity or cost increase. The study/demonstration is done through extensive experimental measurements and numerical simulations. © 2012 IEEE.

A fast 600-V Tandem PiN Schottky (TPS) rectifier with ultra-low on-state voltage

The Tandem PiN Schottky (TPS) rectifier features lowly-doped p-layers in both active and termination regions, and is applied in 600-V rating for the first time. In the active region, the Schottky contact is in series connection with a transparent p-layer, leading to a superior forward performance than the conventional diodes. In addition, due to the benefit of moderate hole injection from the p-layer, the TPS offers a better trade-off between the on-state voltage and the switching speed. The active p-layer also helps to stabilise the Schottky contact, and hence the electrical data distributions are more concentrated. Regarding the floating p-layer in the termination region, its purpose is to reduce the peak electric fields, and the TPS demonstrates a high breakdown voltage with a compact termination width, less than 70% of the state-of-the-art devices on the market. Experimental results have shown that the 600-V TPS rectifier has an ultra-low on-state voltage of 0.98 V at 250 A/cm 2, a fast turn-off time of 75 ns by the standard RG1 test (I F=0.5A, I R=1A, and I RR=0.25A) and a breakdown voltage over 720 V. It is noteworthy that the p-layers in the active and termination regions can be formed at no extra cost for the use of self-alignment process. © 2012 IEEE.

Increasing the open-circuit voltage of photoprotein-based photoelectrochemical cells by manipulation of the vacuum potential of the electrolytes.

The innately highly efficient light-powered separation of charge that underpins natural photosynthesis can be exploited for applications in photoelectrochemistry by coupling nanoscale protein photoreaction centers to man-made electrodes. Planar photoelectrochemical cells employing purple bacterial reaction centers have been constructed that produce a direct current under continuous illumination and an alternating current in response to discontinuous illumination. The present work explored the basis of the open-circuit voltage (V(OC)) produced by such cells with reaction center/antenna (RC-LH1) proteins as the photovoltaic component. It was established that an up to ~30-fold increase in V(OC) could be achieved by simple manipulation of the electrolyte connecting the protein to the counter electrode, with an approximately linear relationship being observed between the vacuum potential of the electrolyte and the resulting V(OC). We conclude that the V(OC) of such a cell is dependent on the potential difference between the electrolyte and the photo-oxidized bacteriochlorophylls in the reaction center. The steady-state short-circuit current (J(SC)) obtained under continuous illumination also varied with different electrolytes by a factor of ~6-fold. The findings demonstrate a simple way to boost the voltage output of such protein-based cells into the hundreds of millivolts range typical of dye-sensitized and polymer-blend solar cells, while maintaining or improving the J(SC). Possible strategies for further increasing the V(OC) of such protein-based photoelectrochemical cells through protein engineering are discussed.

NEMS based logic and memory circuits

Carbon nanotube (CNT) based nano electromechanical system (NEMS) were developed to apply to the logic and the memory circuit. The electrical 'on-off' behavior induced by the mechanical movements of CNTs can promise low power consumption in circuit with very low level leakage current. Additionally, the unique vertical structure of nanotubes allows high integration density for devices. © 2012 IEEE.

Symmetrical low voltage ride-through of a 250 kW Brushless DFIG

The Brushless Doubly-Fed Induction Generator (Brushless DFIG) shows commercial promise for wind power generation due to its lower cost and higher reliability when compared with the conventional Doubly-Fed Induction Generator (DFIG). In the most recent grid codes, wind generators are required to be able to ride through a low voltage fault and meet the reactive current demand from the grid. Hence, a Low-Voltage Ride-Through (LVRT) capability is important for wind generators which are integrated into the grid. In this paper the authors propose a control strategy enabling the Brushless DFIG to successfully ride through a symmetrical voltage dip. The control strategy has been implemented on a 250 kW Brushless DFIG and the experimental results indicate that LVRT is possible without a crowbar.

IGBT series connection under Active Voltage Control with temporary clamp

This paper presents the use of an Active Voltage Control (AVC) technique for balancing the voltages in a series connection of Insulated Gate Bipolar Transistors (IGBTs). The AVC technique can control the switching trajectory of an IGBT according to a pre-set reference signal. In series connections, every series connected IGBT follows the reference and so that the dynamic voltage sharing is achieved. For the static voltage balancing, a temporary clamp technique is introduced. The temporary clamp technique clamps the collector-emitter voltage of all the series connected IGBTs at the ideal voltage so that the IGBTs will share the voltage evenly. © 2012 IEEE.

Dead-time minimisation using active voltage control gate drive for high-power IGBT converters

High-power converters usually need longer dead-times than their lower-power counterparts and a lower switching frequency. Also due to the complicated assembly layout and severe variations in parasitics, in practice the conventional dead-time specific adjustment or compensation for high-power converters is less effective, and usually this process is time-consuming and bespoke. For general applications, minimising or eliminating dead-time in the gate drive technology is a desirable solution. With the growing acceptance of power electronics building blocks (PEBB) and intelligent power modules (IPM), gate drives with intelligent functions are in demand. Smart functions including dead time elimination/minimisation can improve modularity, flexibility and reliability. In this paper, a dead-time minimisation using Active Voltage Control (AVC) gate drive is presented. © 2012 IEEE.

Three-dimensional distribution of Al in high-k metal gate: Impact on transistor voltage threshold

The three-dimensional spatial distribution of Al in the high-k metal gates of metal-oxide-semiconductor field-effect-transistors is measured by atom probe tomography. Chemical distribution is correlated with the transistor voltage threshold (VTH) shift generated by the introduction of a metallic Al layer in the metal gate. After a 1050 °C annealing, it is shown that a 2-Å thick Al layer completely diffuses into oxide layers, while a positive VTH shift is measured. On the contrary, for thicker Al layers, Al precipitation in the metal gate stack is observed and the VTH shift becomes negative. © 2012 American Institute of Physics.

Crowbarless fault ride-through of the brushless doubly fed induction generator in a wind turbine under symmetrical voltage dips

The brushless doubly fed induction generator (BDFIG) shows commercial promise for wind power generation due to its lower cost and higher reliability when compared with the conventional DFIG. In the most recent grid codes, wind generators are required to be able to ride through a low-voltage fault and meet the reactive current demand from the grid. A low-voltage ride-through (LVRT) capability is therefore important for wind generators which are integrated into the grid. In this paper, the authors propose a control strategy enabling the BDFIG to successfully ride through a symmetrical voltage dip. The control strategy has been implemented on a 250-kW BDFIG, and the experimental results indicate that the LVRT is possible without a crowbar. © 1982-2012 IEEE.

Energy recycling from multigigahertz clocks using fully integrated switching converters

Large digital chips use a significant amount of energy to broadcast a low-skew, multigigahertz clock to millions of latches located throughout the chip. Every clock cycle, the large aggregate capacitance of the clock network is charged from the supply and then discharged to ground. Instead of wasting this stored energy, it is possible to recycle the energy by controlling its delivery to another part of the chip using an on-chip dc-dc converter. The clock driver and switching converter circuits share many compatible characteristics that allow them to be merged into a single design and fully integrated on-chip. Our buck converter prototype, manufactured in 90-nm CMOS, provides a proof-of-concept that clock network energy can be recycled to other parts of the chip, thus lowering overall energy consumption. It also confirms that monolithic multigigahertz switching converters utilizing zero-voltage switching can be implemented in deep-submicrometer CMOS. With multigigahertz operation, fully integrated inductors and capacitors use a small amount of chip area with low losses. Combining the clock driver with the power converter can share the large MOSFET drivers necessary as well as being energy and space efficient. We present an analysis of the losses which we confirm by experimentally comparing the merged circuit with a conventional clock driver. © 2012 IEEE.