Electrical characterization of electronic circuits produced by inkjet printing

Dissertação de Mestrado, Engenharia Electrónica e Telecomunicações, Faculdade de Ciências e Tecnologia, Universidade do Algarve, 2014

Detection of explosive vapors using organic thin-film transistors

Field effect transistors (FETs) based on organic materials were investigated as sensors for detecting 2,4,6-trinitrotoluene (TNT) vapors. Several FET devices were fabricated using two types of semiconducting organic materials, solution processed polymers deposited by spin coating and, oligomers (or small molecules) deposited by vacuum sublimation. When vapors of nitroaromatic compounds bind to thin films of organic materials which form the transistor channel, the conductivity of the thin film increases and changes the transistor electrical characteristic. The use of the amplifying properties of the transistor represents a major advantage over conventional techniques based on simple changes of resistance in polymers frequently used in electronic noses.

PEDOT:PSS: un polimero conduttivo organico per lo studio dell'integrità del tessuto cellulare

Questa tesi si inserisce nel campo della Bioelettronica Organica con lo scopo di utilizzare dei transistor elettrochimici (OECT) organici basati sul polimero conduttivo PEDOT:PSS per rilevare l’integrità di un tessuto cellulare e come biosensori di analiti in soluzione. Nella prima parte dell’elaborato, si spiegano le proprietà ed il trasporto di carica dei polimeri coniugati concentrandosi sulle caratteristiche fisico chimiche del PEDOT:PSS, seguito da una trattazione analitica del principio di funzionamento di un OECT. La seconda parte, si concentra sul lavoro sperimentale partendo da una descrizione dei processi di fabbricazione degli OECT, dei metodi di caratterizzazione utilizzati e della progettazione del set-up sperimentale per permettere le misure elettriche nell’incubatore cellulare. In seguito, viene dimostrato l’uso di un OECT completamente a base di PEDOT:PSS come sensore di un neurotrasmettitore (dopamina). In parallelo, il lavoro si è concentrato sull’ottimizzazione dei transistor in termini di formulazione di PEDOT:PSS e di geometria del dispositivo per ottenere tempi di spegnimento veloci compatibili con le risposte cellulari (<300ms). In fase di preparazione alle misure con le cellule si è valutato la funzionalità dell’OECT nelle condizioni di coltura cellulare dimostrando una buona stabilità dei dispositivi. Inoltre, sono stati progettati degli studi di simulazione tramite una membrana porosa per prevedere le risposte dei transistor in presenza di un tessuto cellulare. Partendo dall’esito positivo dei test preliminari, il lavoro si è concluso con il primo esperimento con le cellule tumorali HeLa, in cui si è monitorata la crescita cellulare con immagini ottiche correlate alle misure elettriche. I primi risultati confermano la biocompatibilità dei dispositivi e una risposta elettrica degli OECTs alla presenza delle cellule, aprendo la possibilità di utilizzare questi dispositivi per futuri esperimenti anche con diversi tipi di cellule.

Leakage Temperature Dependency Aware Real-Time Scheduling for Power and Thermal Optimization

Catering to society’s demand for high performance computing, billions of transistors are now integrated on IC chips to deliver unprecedented performances. With increasing transistor density, the power consumption/density is growing exponentially. The increasing power consumption directly translates to the high chip temperature, which not only raises the packaging/cooling costs, but also degrades the performance/reliability and life span of the computing systems. Moreover, high chip temperature also greatly increases the leakage power consumption, which is becoming more and more significant with the continuous scaling of the transistor size. As the semiconductor industry continues to evolve, power and thermal challenges have become the most critical challenges in the design of new generations of computing systems. In this dissertation, we addressed the power/thermal issues from the system-level perspective. Specifically, we sought to employ real-time scheduling methods to optimize the power/thermal efficiency of the real-time computing systems, with leakage/ temperature dependency taken into consideration. In our research, we first explored the fundamental principles on how to employ dynamic voltage scaling (DVS) techniques to reduce the peak operating temperature when running a real-time application on a single core platform. We further proposed a novel real-time scheduling method, “M-Oscillations” to reduce the peak temperature when scheduling a hard real-time periodic task set. We also developed three checking methods to guarantee the feasibility of a periodic real-time schedule under peak temperature constraint. We further extended our research from single core platform to multi-core platform. We investigated the energy estimation problem on the multi-core platforms and developed a light weight and accurate method to calculate the energy consumption for a given voltage schedule on a multi-core platform. Finally, we concluded the dissertation with elaborated discussions of future extensions of our research.

Implementation of dual stack technique for reducing leakage and dynamic power

This paper deals with proposal of a new dual stack approach for reducing both leakage and dynamic powers. The development of digital integrated circuits is challenged by higher power consumption. Thecombination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality ona chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Today leakage power has become anincreasingly important issue in processor hardware and software design. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The leakage power increases astechnology is scaled down. In this paper, we propose a new dual stack approach for reducing both leakage and dynamic powers. Moreover, the novel dual stack approach shows the least speed power product whencompared to the existing methods. All well known approach is “Sleep” in this method we reduce leakage power. The proposed Dual Stack approach we reduce more power leakage. Dual Stack approach uses theadvantage of using the two extra pull-up and two extra pull-down transistors in sleep mode either in OFF state or in ON state. Since the Dual Stack portion can be made common to all logic circuitry, less number of transistors is needed to apply a certain logic circuit.The dual stack approach shows the least speed power product among all methods. The Dual Stack technique provides new ways to designers who require ultra-low leakage power consumption with much less speedpower product.