The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Deposition of Intrinsic a-Si:H by ECR-CVD to Passivate the Crystalline Silicon Heterointerface in HIT Solar Cells

We have deposited intrinsic amorphous silicon (a-Si:H) using the electron cyclotron resonance (ECR) chemical vapor deposition technique in order to analyze the a-Si:H/c-Si heterointerface and assess the possible application in heterojunction with intrinsic thin layer (HIT) solar cells. Physical characterization of the deposited films shows that the hydrogen content is in the 15-30% range, depending on deposition temperature. The optical bandgap value is always comprised within the range 1.9- 2.2 eV. Minority carrier lifetime measurements performed on the heterostructures reach high values up to 1.3 ms, indicating a well-passivated a-Si:H/c-Si heterointerface for deposition temperatures as low as 100°C. In addition, we prove that the metal-oxide- semiconductor conductance method to obtain interface trap distribution can be applied to the a-Si:H/c-Si heterointerface, since the intrinsic a-Si:H layer behaves as an insulator at low or negative bias. Values for the minimum of D_it as low as 8 × 10^10 cm^2 · eV^-1 were obtained for our samples, pointing to good surface passivation properties of ECR-deposited a-Si:H for HIT solar cell applications.

Limitations of high pressure sputtering for amorphous silicon deposition

Amorphous silicon thin films were deposited using the high pressure sputtering (HPS) technique to study the influence of deposition parameters on film composition, presence of impurities, atomic bonding characteristics and optical properties. An optical emission spectroscopy (OES) system has been used to identify the different species present in the plasma in order to obtain appropriate conditions to deposit high purity films. Composition measurements in agreement with the OES information showed impurities which critically depend on the deposition rate and on the gas pressure. We prove that films deposited at the highest RF power and 3.4 × 10^−2 mbar, exhibit properties as good as the ones of the films deposited by other more standard techniques.

Room temperature photo-response of titanium supersaturated silicon at energies over the bandgap

Silicon samples were implanted with high Ti doses and subsequently processed with the pulsed-laser melting technique. The electronic transport properties in the 15–300 K range and the room temperature spectral photoresponse at energies over the bandgap were measured. Samples with Ti concentration below the insulator-metal (I-M) transition limit showed a progressive reduction of the carrier lifetime in the implanted layer as Ti dose is increased. However, when the Ti concentration exceeded this limit, an extraordinary recovery of the photoresponse was measured. This result supports the theory of intermediate band materials and is of utmost relevance for photovoltaic cells and Si-based detectors.

Post-CMOS compatible high-throughput fabrication of AIN-based piezoelectric microcantilevers

A post-complementary metal oxide semiconductor (CMOS) compatible microfabrication process of piezoelectric cantilevers has been developed. The fabrication process is suitable for standard silicon technology and provides low-cost and high-throughput manufacturing. This work reports design, fabrication and characterization of piezoelectric cantilevers based on aluminum nitride (AlN) thin films synthesized at room temperature. The proposed microcantilever system is a sandwich structure composed of chromium (Cr) electrodes and a sputtered AlN film. The key issue for cantilever fabrication is the growth at room temperature of the AlN layer by reactive sputtering, making possible the innovative compatibility of piezoelectric MEMS devices with CMOS circuits already processed. AlN and Cr have been etched by inductively coupled plasma (ICP) dry etching using a BCl3–Cl2–Ar plasma chemistry. As part of the novelty of the post-CMOS micromachining process presented here, a silicon Si (1 0 0) wafer has been used as substrate as well as the sacrificial layer used to release the microcantilevers. In order to achieve this, the Si surface underneath the structure has been wet etched using an HNA (hydrofluoric acid + nitric acid + acetic acid) based solution. X-ray diffraction (XRD) characterization indicated the high crystalline quality of the AlN film. An atomic force microscope (AFM) has been used to determine the Cr electrode surface roughness. The morphology of the fabricated devices has been studied by scanning electron microscope (SEM). The cantilevers have been piezoelectrically actuated and their out-of-plane vibration modes were detected by vibrometry.

Electrical characterization of CVD diamond-n(+) silicon junctions

The electrical characteristics of CVD-diamond/n(+)-Si heterojunction devices are reported. Below 250 K the diodes show an unusual inversion of their rectification properties. This behavior is attributed to an enhanced tunneling component due to interface states, which change their occupation with the applied bias. The temperature dependence of the loss tangent shows two relaxation processes with different activation energies. These processes are likely related with two parallel charge transport mechanisms, one through the diamond grain, and the other through the grain boundary. (C) 2001 Elsevier Science B.V. Ah rights reserved.

Electrical characterization of pn-junctions of PPV and silicon

Poly(phenylene vinylene) (PPV) grown via the precursor route, deposited on top of heavily doped n-type silicon, was studied using electrical measurement techniques. The results are compared to PPV grown via deposition of soluble derivative (MEH-PPV). The two types are very similar. They have comparable free carrier densities and both show minority-carrier effects. The activation energy found via the loss tangent is 0.13 eV. The effect of exposure to oxygen is visible in the capacitance and the current.

IN-SITU ELECTRICAL, MECHANICAL AND ELECTROCHEMICAL CHARACTERIZATIONS OF ONE-DIMENSIONAL NANOSTRUCTURES

One-dimensional nanostructures initiated new aspects to the materials applications due to their superior properties compared to the bulk materials. Properties of nanostructures have been characterized by many techniques and used for various device applications. However, simultaneous correlation between the physical and structural properties of these nanomaterials has not been widely investigated. Therefore, it is necessary to perform in-situ study on the physical and structural properties of nanomaterials to understand their relation. In this work, we will use a unique instrument to perform real time atomic force microscopy (AFM) and scanning tunneling microscopy (STM) of nanomaterials inside a transmission electron microscopy (TEM) system. This AFM/STM-TEM system is used to investigate the mechanical, electrical, and electrochemical properties of boron nitride nanotubes (BNNTs) and Silicon nanorods (SiNRs). BNNTs are one of the subjects of this PhD research due to their comparable, and in some cases superior, properties compared to carbon nanotubes. Therefore, to further develop their applications, it is required to investigate these characteristics in atomic level. In this research, the mechanical properties of multi-walled BNNTs were first studied. Several tests were designed to study and characterize their real-time deformation behavior to the applied force. Observations revealed that BNNTs possess highly flexible structures under applied force. Detailed studies were then conducted to understand the bending mechanism of the BNNTs. Formations of reversible ripples were observed and described in terms of thermodynamic energy of the system. Fracture failure of BNNTs were initiated at the outermost walls and characterized to be brittle. Second, the electrical properties of individual BNNTs were studied. Results showed that the bandgap and electronic properties of BNNTs can be engineered by means of applied strain. It was found that the conductivity, electron concentration and carrier mobility of BNNTs can be tuned as a function of applied stress. Although, BNNTs are considered to be candidate for field emission applications, observations revealed that their properties degrade upon cycles of emissions. Results showed that due to the high emission current density, the temperature of the sample was increased and reached to the decomposition temperature at which the B-N bonds start to break. In addition to BNNTs, we have also performed in-situ study on the electrochemical properties of silicon nanorods (SiNRs). Specifically, lithiation and delithiation of SiNRs were studied by our STM-TEM system. Our observations showed the direct formation of Li22Si5 phases as a result of lithium intercalation. Radial expansion of the anode materials were observed and characterized in terms of size-scale. Later, the formation and growth of the lithium fibers on the surface of the anode materials were observed and studied. Results revealed the formation of lithium islands inside the ionic liquid electrolyte which then grew as Li dendrite toward the cathode material.

CO-ELECTROPHORETIC DEPOSITION OF LIQUID METAL AND SILICON FOR LITHIUM-ION BATTERY APPLICATION

A low cost electrophoretic deposition (EPD) process was successfully used for liquid metal thin film deposition with a high depositing rate of 0.6 µ/min. Furthermore, silicon nano-powder and liquid metal were then simultaneously deposited as the negative electrode of lithium-ion battery by a technology called co-EPD. The liquid metal was hoping to act as the matrix for silicon particles during lithium ion insertion and distraction. Half-cell testing was performed using as prepared co-EPD sample. An initial discharge capacity of 1500 mAh/g was reported for nano-silicon and galinstan electrode, although the capacity fading issue of these samples was also observed.

THE EFFECT OF ANNEALING ON AMORPHOUS SILICON BASED SOLAR PHOTOVOLTAIC THERMAL SYSTEM (PV/T) AND APPROPRIATE GLOBAL DISPATCH STRATEGIES

Previous work has shown that high-temperature short-term spike thermal annealing of hydrogenated amorphous silicon (a-Si:H) photovoltaic thermal (PVT) systems results in higher electrical energy output. The relationship between temperature and performance of a-Si:H PVT is not simple as high temperatures during thermal annealing improves the immediate electrical performance following an anneal, but during the anneal it creates a marked drop in electrical performance. In addition, the power generation of a-Si:H PVT depends on both the environmental conditions and the Staebler-Wronski Effect kinetics. In order to improve the performance of a-Si:H PVT systems further, this paper reports on the effect of various dispatch strategies on system electrical performance. Utilizing experimental results from thermal annealing, an annealing model simulation for a-Si:Hbased PVT was developed and applied to different cities in the U.S. to investigate potential geographic effects on the dispatch optimization of the overall electrical PVT systems performance and annual electrical yield. The results showed that spike thermal annealing once per day maximized the improved electrical energy generation. In the outdoor operating condition this ideal behavior deteriorates and optimization rules are required to be implemented.

Silicon Photonic Device for Wavelength Sensing and Monitoring

Over the last decade advances and innovations from Silicon Photonics technology were observed in the telecommunications and computing industries. This technology which employs Silicon as an optical medium, relies on current CMOS micro-electronics fabrication processes to enable medium scale integration of many nano-photonic devices to produce photonic integrated circuitry. However, other fields of research such as optical sensor processing can benefit from silicon photonics technology, specially in sensors where the physical measurement is wavelength encoded. In this research work, we present a design and application of a thermally tuned silicon photonic device as an optical sensor interrogator. The main device is a micro-ring resonator filter of 10 $\mu m$ of diameter. A photonic design toolkit was developed based on open source software from the research community. With those tools it was possible to estimate the resonance and spectral characteristics of the filter. From the obtained design parameters, a 7.8 x 3.8 mm optical chip was fabricated using standard micro-photonics techniques. In order to tune a ring resonance, Nichrome micro-heaters were fabricated on top of the device. Some fabricated devices were systematically characterized and their tuning response were determined. From measurements, a ring resonator with a free-spectral-range of 18.4 nm and with a bandwidth of 0.14 nm was obtained. Using just 5 mA it was possible to tune the device resonance up to 3 nm. In order to apply our device as a sensor interrogator in this research, a model of wavelength estimation using time interval between peaks measurement technique was developed and simulations were carried out to assess its performance. To test the technique, an experiment using a Fiber Bragg grating optical sensor was set, and estimations of the wavelength shift of this sensor due to axial strains yield an error within 22 pm compared to measurements from spectrum analyzer. Results from this study implies that signals from FBG sensors can be processed with good accuracy using a micro-ring device with the advantage of ts compact size, scalability and versatility. Additionally, the system also has additional applications such as processing optical wavelength shifts from integrated photonic sensors and to be able to track resonances from laser sources.

A comparative analysis of the characterization methods for submicron silicon waveguide propagation loss

An important parameter in integrated optical device is the propagation loss of the waveguide. Its characterization gives the information of the fabrication quality as well as the information of other passive devices on the chip as it is the basic building block of the passive devices. Although, over the last three decades many methods have been developed, there is not a single standard present yet. This paper presents a comparative analysis of the methods existing from the past as well as methods developed very recently in order to provide a complete picture of the pros and cons of different types of methods and from this comparison the best method is suggested according to the authors opinion. To support the claim, apart from the analytical comparison, this paper also presents a comparison performed with the experimental results between the suggested best method which is recently proposed by Massachusetts Institute of Technology (MIT) researchers based on undercoupled all-pass microring structure and the popular cut-back method.

Insulator-to-metal transition in vanadium supersaturated silicon: variable-range hopping and Kondo effect signatures

We report the observation of the insulator-to-metal transition in crystalline silicon samples supersaturated with vanadium. Ion implantation followed by pulsed laser melting and rapid resolidification produce high quality single-crystalline silicon samples with vanadium concentrations that exceed equilibrium values in more than 5 orders of magnitude. Temperature-dependent analysis of the conductivity and Hall mobility values for temperatures from 10K to 300K indicate that a transition from an insulating to a metallic phase is obtained at a vanadium concentration between 1.1 × 10^(20) and 1.3 × 10^(21) cm^(−3) . Samples in the insulating phase present a variable-range hopping transport mechanism with a Coulomb gap at the Fermi energy level. Electron wave function localization length increases from 61 to 82 nm as the vanadium concentration increases in the films, supporting the theory of impurity band merging from delocalization of levels states. On the metallic phase, electronic transport present a dispersion mechanism related with the Kondo effect, suggesting the presence of local magnetic moments in the vanadium supersaturated silicon material.

High Frequency Class DE Converter Using a Multilayer Coreless PCB Transformer

In modern power electronics equipment, it is desirable to design a low profile, high power density, and fast dynamic response converter. Increases in switching frequency reduce the size of the passive components such as transformers, inductors, and capacitors which results in compact size and less requirement for the energy storage. In addition, the fast dynamic response can be achieved by operating at high frequency. However, achieving high frequency operation while keeping the efficiency high, requires new advanced devices, higher performance magnetic components, and new circuit topology. These are required to absorb and utilize the parasitic components and also to mitigate the frequency dependent losses including switching loss, gating loss, and magnetic loss. Required performance improvements can be achieved through the use of Radio Frequency (RF) design techniques. To reduce switching losses, resonant converter topologies like resonant RF amplifiers (inverters) combined with a rectifier are the effective solution to maintain high efficiency at high switching frequencies through using the techniques such as device parasitic absorption, Zero Voltage Switching (ZVS), Zero Current Switching (ZCS), and a resonant gating. Gallium Nitride (GaN) device technologies are being broadly used in RF amplifiers due to their lower on- resistance and device capacitances compared with silicon (Si) devices. Therefore, this kind of semiconductor is well suited for high frequency power converters. The major problems involved with high frequency magnetics are skin and proximity effects, increased core and copper losses, unbalanced magnetic flux distribution generating localized hot spots, and reduced coupling coefficient. In order to eliminate the magnetic core losses which play a crucial role at higher operating frequencies, a coreless PCB transformer can be used. Compared to the conventional wire-wound transformer, a planar PCB transformer in which the windings are laid on the Printed Board Circuit (PCB) has a low profile structure, excellent thermal characteristics, and ease of manufacturing. Therefore, the work in this thesis demonstrates the design and analysis of an isolated low profile class DE resonant converter operating at 10 MHz switching frequency with a nominal output of 150 W. The power stage consists of a class DE inverter using GaN devices along with a sinusoidal gate drive circuit on the primary side and a class DE rectifier on the secondary side. For obtaining the stringent height converter, isolation is provided by a 10-layered coreless PCB transformer of 1:20 turn’s ratio. It is designed and optimized using 3D Finite Element Method (FEM) tools and radio frequency (RF) circuit design software. Simulation and experimental results are presented for a 10-layered coreless PCB transformer operating in 10 MHz.

Isolating the photovoltaic junction: atomic layer deposited TiO2-RuO2 alloy Schottky contacts for silicon photoanodes

We synthesized nanoscale TiO2-RuO2 alloys by atomic layer deposition (ALD) that possess a high work function and are highly conductive. As such, they function as good Schottky contacts to extract photogenerated holes from n-type silicon while simultaneously interfacing with water oxidation catalysts. The ratio of TiO2 to RuO2 can be precisely controlled by the number of ALD cycles for each precursor. Increasing the composition above 16% Ru sets the electronic conductivity and the metal work function. No significant Ohmic loss for hole transport is measured as film thickness increases from 3 to 45 nm for alloy compositions >= 16% Ru. Silicon photoanodes with a 2 nm SiO2 layer that are coated by these alloy Schottky contacts having compositions in the range of 13-46% Ru exhibit average photovoltages of 525 mV, with a maximum photovoltage of 570 mV achieved. Depositing TiO2-RuO2 alloys on nSi sets a high effective work function for the Schottky junction with the semiconductor substrate, thus generating a large photovoltage that is isolated from the properties of an overlying oxygen evolution catalyst or protection layer.