996 resultados para Silicon wafer
Resumo:
Over the past 20 years, ferroelectric liquid crystal over silicon (FLCOS) devices have made a wide impact on applications as diverse as optical correlation and holographic projection. To cover the entire gamut of this technology would be difficult and long winded; hence, this paper describes the significant developments of FLCOS within the Engineering Department at the University of Cambridge.The purpose of this paper is to highlight the key issues in fabricating silicon backplane spatial light modulators (SLMs) and to indicate ways in which the technology can be fabricated using cheap, low-density production and manufacturability. Three main devices have been fabricated as part of several research programmes and are documented in this paper. The fast bitplane SLM and the reconfigurable optical switches for aerospace and telecommunications systems (ROSES) SLM will form the basis of a case study to outline the overall processes involved. There is a great deal of commonality in the fabrication processes for all three devices, which indicates their potential strength and demonstrates that these processes can be made independent of the SLMs that are being assembled. What is described is a generic process that can be applied to any silicon backplane SLM on a die-by-die basis. There are hundreds of factors that can affect the yield in a manufacturing process and the purpose of a good process design procedure is to minimise these factors. One of the most important features in designing a process is fabrication experience, as so many of the lessons in this business can only be learned this way. We are working with the advantage of knowing the mistakes already made in the flat panel display industry, but we are also faced with the fact that those mistakes took many years and many millions of dollars to make.The fabrication process developed here originates and adapts earlier processes from various groups around the world. There are also a few totally new processes that have now been adopted by others in the field. Many, such as the gluing process, are still on-going and have to be worked on more before they will fully suit 'manufacturability'. © 2012 Copyright Taylor and Francis Group, LLC.
Resumo:
A method to measure the optical response across the surface of a phase-only liquid crystal on silicon device using binary phase gratings is described together with a procedure to compensate its spatial optical phase variation. As a result, the residual power between zero and the minima of the first diffraction order for a binary grating can be reduced by more than 10 dB, from -15.98 dB to -26.29 dB. This phase compensation method is also shown to be useful in nonbinary cases. A reduction in the worst crosstalk by 5.32 dB can be achieved when quantized blazed gratings are used.
Resumo:
Process simulation programs are valuable in generating accurate impurity profiles. Apart from accuracy the programs should also be efficient so as not to consume vast computer memory. This is especially true for devices and circuits of VLSI complexity. In this paper a remeshing scheme to make the finite element based solution of the non-linear diffusion equation more efficient is proposed. A remeshing scheme based on comparing the concentration values of adjacent node was then implemented and found to remove the problems of oscillation.
Resumo:
Metal-catalyst-free chemical vapor deposition (CVD) of large area uniform nanocrystalline graphene on oxidized silicon substrates is demonstrated. The material grows slowly, allowing for thickness control down to monolayer graphene. The as-grown thin films are continuous with no observable pinholes, and are smooth and uniform across whole wafers, as inspected by optical-, scanning electron-, and atomic force microscopy. The sp 2 hybridized carbon structure is confirmed by Raman spectroscopy. Room temperature electrical measurements show ohmic behavior (sheet resistance similar to exfoliated graphene) and up to 13 of electric-field effect. The Hall mobility is ∼40 cm 2/Vs, which is an order of magnitude higher than previously reported values for nanocrystalline graphene. Transmission electron microscopy, Raman spectroscopy, and transport measurements indicate a graphene crystalline domain size ∼10 nm. The absence of transfer to another substrate allows avoidance of wrinkles, holes, and etching residues which are usually detrimental to device performance. This work provides a broader perspective of graphene CVD and shows a viable route toward applications involving transparent electrodes. © 2012 American Institute of Physics.
Resumo:
The electrical and structural characteristics of tantalum-titanium bilayers on silicon reacted by electron beam heating have been investigated over a wide range of temperature and time conditions. The reacted layers exhibit low sheet resistance and stable electrical characteristics up to at least 1100℃. Titanium starts reacting from 750℃ onwards for 100 milliseconds reaction times whereas tantalum starts reacting only above 900℃ for such short reaction times. RBS results confirm that silicon is the major diffusing species and there is no evidence for the formation of ternary silicides. Reactions have also been explored on millisecond time scales by non-isothermal heating.
Resumo:
Trapped electrons, located close to the channel of a transistor, are promising as data storage elements in non-classical information processing. Cryogenic microwave spectroscopy has shown that these electrons give rise to high quality factor resonances in the drain current and a post excitation dynamic behaviour that is related to the system lifetime. Using a floating poly-silicon gate transistor, single shot spectroscopy is performed to characterise the dynamic behaviour during excitation. This behaviour is seen to be dominated by the decay of the transient component, which gives rise to oscillations around the high quality factor resonance. © 2012 American Institute of Physics.
Resumo:
This paper demonstrates and discusses novel "three dimensional" silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures. The proposed designs are both compact and effective in safely distributing the electrostatic potential away from the active device area. The designs are based on the utilization of existing layers in the device fabrication line, hence resulting in no extra complexity or cost increase. The study/demonstration is done through extensive experimental measurements and numerical simulations. © 2012 IEEE.
Resumo:
In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models. © 2012 IEEE.
Resumo:
Ammonia (NH 3) plasma pretreatment is used to form and temporarily reduce the mobility of Ni, Co, or Fe nanoparticles on boron-doped mono- and poly-crystalline silicon. X-ray photoemission spectroscopy proves that NH 3 plasma nitrides the Si supports during nanoparticle formation which prevents excessive nanoparticle sintering/diffusion into the bulk of Si during carbon nanotube growth by chemical vapour deposition. The nitridation of Si thus leads to nanotube vertical alignment and the growth of nanotube forests by root growth mechanism. © 2012 American Institute of Physics.