974 resultados para SILICON CMOS


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BACKGROUND AND AIMS: Silicon has been shown to enhance the resistance of plants to fungal and bacterial pathogens. Here, the effect of potassium silicate was assessed on two cotton (Gossypium hirsutum) cultivars subsequently inoculated with Fusarium oxysporum f. sp. vasinfectum (Fov). Sicot 189 is moderately resistant whilst Sicot F-1 is the second most resistant commercial cultivar presently available in Australia. METHODS: Transmission and light microscopy were used to compare cellular modifications in root cells after these different treatments. The accumulation of phenolic compounds and lignin was measured. KEY RESULTS: Cellular alterations including the deposition of electron-dense material, degradation of fungal hyphae and occlusion of endodermal cells were more rapidly induced and more intense in endodermal and vascular regions of Sicot F-1 plants supplied with potassium silicate followed by inoculation with Fov than in similarly treated Sicot 189 plants or in silicate-treated plants of either cultivar not inoculated with Fov. Significantly more phenolic compounds were present at 7 d post-infection (dpi) in root extracts of Sicot F-1 plants treated with potassium silicate followed by inoculation with Fov compared with plants from all other treatments. The lignin concentration at 3 dpi in root material from Sicot F-1 treated with potassium silicate and inoculated with Fov was significantly higher than that from water-treated and inoculated plants. CONCLUSIONS: This study demonstrates that silicon treatment can affect cellular defence responses in cotton roots subsequently inoculated with Fov, particularly in Sicot F-1, a cultivar with greater inherent resistance to this pathogen. This suggests that silicon may interact with or initiate defence pathways faster in this cultivar than in the less resistant cultivar.

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Analysis methods for electrochemical etching baths consisting of various concentrations of hydrofluoric acid (HF) and an additional organic surface wetting agent are presented. These electrolytes are used for the formation of meso- and macroporous silicon. Monitoring the etching bath composition requires at least one method each for the determination of the HF concentration and the organic content of the bath. However, it is a precondition that the analysis equipment withstands the aggressive HF. Titration and a fluoride ion-selective electrode are used for the determination of the HF and a cuvette test method for the analysis of the organic content, respectively. The most suitable analysis method is identified depending on the components in the electrolyte with the focus on capability of resistance against the aggressive HF.

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Charge carrier lifetime measurements in bulk or unfinished photovoltaic (PV) materials allow for a more accurate estimate of power conversion efficiency in completed solar cells. In this work, carrier lifetimes in PV- grade silicon wafers are obtained by way of quasi-steady state photoconductance measurements. These measurements use a contactless RF system coupled with varying narrow spectrum input LEDs, ranging in wavelength from 460 nm to 1030 nm. Spectral dependent lifetime measurements allow for determination of bulk and surface properties of the material, including the intrinsic bulk lifetime and the surface recombination velocity. The effective lifetimes are fit to an analytical physics-based model to determine the desired parameters. Passivated and non-passivated samples are both studied and are shown to have good agreement with the theoretical model.

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We have deposited intrinsic amorphous silicon (a-Si:H) using the electron cyclotron resonance (ECR) chemical vapor deposition technique in order to analyze the a-Si:H/c-Si heterointerface and assess the possible application in heterojunction with intrinsic thin layer (HIT) solar cells. Physical characterization of the deposited films shows that the hydrogen content is in the 15-30% range, depending on deposition temperature. The optical bandgap value is always comprised within the range 1.9- 2.2 eV. Minority carrier lifetime measurements performed on the heterostructures reach high values up to 1.3 ms, indicating a well-passivated a-Si:H/c-Si heterointerface for deposition temperatures as low as 100°C. In addition, we prove that the metal-oxide- semiconductor conductance method to obtain interface trap distribution can be applied to the a-Si:H/c-Si heterointerface, since the intrinsic a-Si:H layer behaves as an insulator at low or negative bias. Values for the minimum of D_it as low as 8 × 10^10 cm^2 · eV^-1 were obtained for our samples, pointing to good surface passivation properties of ECR-deposited a-Si:H for HIT solar cell applications.

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Amorphous silicon thin films were deposited using the high pressure sputtering (HPS) technique to study the influence of deposition parameters on film composition, presence of impurities, atomic bonding characteristics and optical properties. An optical emission spectroscopy (OES) system has been used to identify the different species present in the plasma in order to obtain appropriate conditions to deposit high purity films. Composition measurements in agreement with the OES information showed impurities which critically depend on the deposition rate and on the gas pressure. We prove that films deposited at the highest RF power and 3.4 × 10^−2 mbar, exhibit properties as good as the ones of the films deposited by other more standard techniques.

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Silicon samples were implanted with high Ti doses and subsequently processed with the pulsed-laser melting technique. The electronic transport properties in the 15–300 K range and the room temperature spectral photoresponse at energies over the bandgap were measured. Samples with Ti concentration below the insulator-metal (I-M) transition limit showed a progressive reduction of the carrier lifetime in the implanted layer as Ti dose is increased. However, when the Ti concentration exceeded this limit, an extraordinary recovery of the photoresponse was measured. This result supports the theory of intermediate band materials and is of utmost relevance for photovoltaic cells and Si-based detectors.

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Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking.

In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy efficiency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The receiver sensitivity is measured to be -8.8dBm at 32Gb/s.

Next, on the optical transmitter side, three new techniques will be presented. First one is a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop. As a first proof of concept, a prototype has been fabricated and measured up to 10Gb/s. The second technique is thermal stabilization of micro-ring resonator modulators through direct measurement of temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. A prototype is fabricated and a closed-loop feedback system is demonstrated to operate at 20Gb/s in the presence of temperature fluctuations. The third technique is a switched-capacitor based pre-emphasis technique designed to extend the inherently low bandwidth of carrier injection micro-ring modulators. A measured prototype of the optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit based on the monolithic PTAT sensor consumes 0.29mW.

Lastly, a first-order frequency synthesizer that is suitable for high-speed on-chip clock generation will be discussed. The proposed design features an architecture combining an LC quadrature VCO, two sample-and-holds, a PI, digital coarse-tuning, and rotational frequency detection for fine-tuning. In addition to an electrical reference clock, as an extra feature, the prototype chip is capable of receiving a low jitter optical reference clock generated by a high-repetition-rate mode-locked laser. The output clock at 8GHz has an integrated RMS jitter of 490fs, peak-to-peak periodic jitter of 2.06ps, and total RMS jitter of 680fs. The reference spurs are measured to be –64.3dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.

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The electrical characteristics of CVD-diamond/n(+)-Si heterojunction devices are reported. Below 250 K the diodes show an unusual inversion of their rectification properties. This behavior is attributed to an enhanced tunneling component due to interface states, which change their occupation with the applied bias. The temperature dependence of the loss tangent shows two relaxation processes with different activation energies. These processes are likely related with two parallel charge transport mechanisms, one through the diamond grain, and the other through the grain boundary. (C) 2001 Elsevier Science B.V. Ah rights reserved.

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Poly(phenylene vinylene) (PPV) grown via the precursor route, deposited on top of heavily doped n-type silicon, was studied using electrical measurement techniques. The results are compared to PPV grown via deposition of soluble derivative (MEH-PPV). The two types are very similar. They have comparable free carrier densities and both show minority-carrier effects. The activation energy found via the loss tangent is 0.13 eV. The effect of exposure to oxygen is visible in the capacitance and the current.

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A low cost electrophoretic deposition (EPD) process was successfully used for liquid metal thin film deposition with a high depositing rate of 0.6 µ/min. Furthermore, silicon nano-powder and liquid metal were then simultaneously deposited as the negative electrode of lithium-ion battery by a technology called co-EPD. The liquid metal was hoping to act as the matrix for silicon particles during lithium ion insertion and distraction. Half-cell testing was performed using as prepared co-EPD sample. An initial discharge capacity of 1500 mAh/g was reported for nano-silicon and galinstan electrode, although the capacity fading issue of these samples was also observed.

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Previous work has shown that high-temperature short-term spike thermal annealing of hydrogenated amorphous silicon (a-Si:H) photovoltaic thermal (PVT) systems results in higher electrical energy output. The relationship between temperature and performance of a-Si:H PVT is not simple as high temperatures during thermal annealing improves the immediate electrical performance following an anneal, but during the anneal it creates a marked drop in electrical performance. In addition, the power generation of a-Si:H PVT depends on both the environmental conditions and the Staebler-Wronski Effect kinetics. In order to improve the performance of a-Si:H PVT systems further, this paper reports on the effect of various dispatch strategies on system electrical performance. Utilizing experimental results from thermal annealing, an annealing model simulation for a-Si:Hbased PVT was developed and applied to different cities in the U.S. to investigate potential geographic effects on the dispatch optimization of the overall electrical PVT systems performance and annual electrical yield. The results showed that spike thermal annealing once per day maximized the improved electrical energy generation. In the outdoor operating condition this ideal behavior deteriorates and optimization rules are required to be implemented.

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An important parameter in integrated optical device is the propagation loss of the waveguide. Its characterization gives the information of the fabrication quality as well as the information of other passive devices on the chip as it is the basic building block of the passive devices. Although, over the last three decades many methods have been developed, there is not a single standard present yet. This paper presents a comparative analysis of the methods existing from the past as well as methods developed very recently in order to provide a complete picture of the pros and cons of different types of methods and from this comparison the best method is suggested according to the authors opinion. To support the claim, apart from the analytical comparison, this paper also presents a comparison performed with the experimental results between the suggested best method which is recently proposed by Massachusetts Institute of Technology (MIT) researchers based on undercoupled all-pass microring structure and the popular cut-back method.

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We report the observation of the insulator-to-metal transition in crystalline silicon samples supersaturated with vanadium. Ion implantation followed by pulsed laser melting and rapid resolidification produce high quality single-crystalline silicon samples with vanadium concentrations that exceed equilibrium values in more than 5 orders of magnitude. Temperature-dependent analysis of the conductivity and Hall mobility values for temperatures from 10K to 300K indicate that a transition from an insulating to a metallic phase is obtained at a vanadium concentration between 1.1 × 10^(20) and 1.3 × 10^(21) cm^(−3) . Samples in the insulating phase present a variable-range hopping transport mechanism with a Coulomb gap at the Fermi energy level. Electron wave function localization length increases from 61 to 82 nm as the vanadium concentration increases in the films, supporting the theory of impurity band merging from delocalization of levels states. On the metallic phase, electronic transport present a dispersion mechanism related with the Kondo effect, suggesting the presence of local magnetic moments in the vanadium supersaturated silicon material.

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We synthesized nanoscale TiO2-RuO2 alloys by atomic layer deposition (ALD) that possess a high work function and are highly conductive. As such, they function as good Schottky contacts to extract photogenerated holes from n-type silicon while simultaneously interfacing with water oxidation catalysts. The ratio of TiO2 to RuO2 can be precisely controlled by the number of ALD cycles for each precursor. Increasing the composition above 16% Ru sets the electronic conductivity and the metal work function. No significant Ohmic loss for hole transport is measured as film thickness increases from 3 to 45 nm for alloy compositions >= 16% Ru. Silicon photoanodes with a 2 nm SiO2 layer that are coated by these alloy Schottky contacts having compositions in the range of 13-46% Ru exhibit average photovoltages of 525 mV, with a maximum photovoltage of 570 mV achieved. Depositing TiO2-RuO2 alloys on nSi sets a high effective work function for the Schottky junction with the semiconductor substrate, thus generating a large photovoltage that is isolated from the properties of an overlying oxygen evolution catalyst or protection layer.

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Silicon photoanodes protected by atomic layer deposited (ALD) TiO2 show promise as components of water splitting devices that may enable the large-scale production of solar fuels and chemicals. Minimizing the resistance of the oxide corrosion protection layer is essential for fabricating efficient devices with good fill factor. Recent literature reports have shown that the interfacial SiO2 layer, interposed between the protective ALD-TiO2 and the Si anode, acts as a tunnel oxide that limits hole conduction from the photoabsorbing substrate to the surface oxygen evolution catalyst. Herein, we report a significant reduction of bilayer resistance, achieved by forming stable, ultrathin (<1.3 nm) SiO2 layers, allowing fabrication of water splitting photoanodes with hole conductances near the maximum achievable with the given catalyst and Si substrate. Three methods for controlling the SiO2 interlayer thickness on the Si(100) surface for ALD-TiO2 protected anodes were employed: (1) TiO2 deposition directly on an HF-etched Si(100) surface, (2) TiO2 deposition after SiO2 atomic layer deposition on an HF-etched Si(100) surface, and (3) oxygen scavenging, post-TiO2 deposition to decompose the SiO2 layer using a Ti overlayer. Each of these methods provides a progressively superior means of reliably thinning the interfacial SiO2 layer, enabling the fabrication of efficient and stable water oxidation silicon anodes.