985 resultados para William P. Whelihan III


Relevância:

40.00% 40.00%

Publicador:

Resumo:

Appendix IV: The literary remains of "Ald Hoggart," the painter's uncle, p. 206-209.

Relevância:

40.00% 40.00%

Publicador:

Resumo:

Trägerband: Ms. Barth. 56; Vorbesitzer: Johann Qwentin von Ortenberg; Jungo Frosch; Bartholomaeusstift Frankfurt am Main

Relevância:

40.00% 40.00%

Publicador:

Resumo:

Trägerband: 'Sc. occ. 131'

Relevância:

40.00% 40.00%

Publicador:

Resumo:

Trägerband: 'L. lin.8. N.40'; Vorbesitzer: Karmeliterkloster Frankfurt am Main

Relevância:

40.00% 40.00%

Publicador:

Resumo:

Trägerband: Inc. qu. 1011

Relevância:

40.00% 40.00%

Publicador:

Resumo:

Trägerband: Inc. qu. 1290; Vorbesitzer: Dominikanerkloster Frankfurt am Main

Relevância:

40.00% 40.00%

Publicador:

Resumo:

Este artículo pretende ser complemento y continuación de mis anteriores trabajos sobre la figura de Petrus Hispanus O. P., Auctor Summularum. Comienzo presentando algunos nuevos documentos relacionados con las cuestiones ya examinadas en mis artículos de 1997 y 2001. A continuación, me ocupo de las cuestiones aplazadas en el artículo de 2001: los problemas relativos a la figura de “Petrus Ferrandi” y su posible relación con el “auctor Summularum”, así como los argumentos de Tugwell contra la hiptesis de la posible identidad de estas dos figuras, examinados ahora desde la perspectiva del autor de la Legenda prima. Tras analizar testimonios procedentes de muy diversos ámbitos, afirmo, por una parte, que la hiptesis de la identidad entre “Petrus Ferrandi” y “Petrus Hispanus” podría ser correcta y, por otra parte, que no hay argumentos concluyentes que obliguen a afirmar con seguridad que el autor de la Legenda prima es Pedro Ferrando. Aunque los análisis no permiten por el momento determinar si es “Petrus Alfonsi” o “Petrus Ferrandi” el “auctor Summularum”, los testimonios recogidos y las conexiones establecidas contribuirán, sin duda, a orientar futuras investigaciones en torno a la figura de “Petrus Hispanus”.

Relevância:

40.00% 40.00%

Publicador:

Resumo:

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of Inx≥0.53Ga1-xAs/In0.52Al0.48As and Inx≥0.1Ga1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cmp>2p>/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In0.85Ga0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (Lside) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH4)2S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al2O3/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10p>12p>cmp>-2p>eVp>-1p> in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (Id,sat=1.14mA/mm), double peaked transconductance (gm=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (Ron=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of Id,sat (11×), gm (5.5×) and Ron (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (Lside) from 1μm down to 70nm improved Id,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In0.3Ga0.7Sb-channel (Id,sat=49.4mA/mm, gm=12.3mS/mm, Ron=31.7kΩ.μm) and In0.4Ga0.6Sb-channel (Id,sat=38mA/mm, gm=11.9mS/mm, Ron=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Relevância:

30.00% 30.00%

Publicador:

Resumo:

Films of piezoelectric PVDF and P(VDF-TrFE) were exposed to vacuum UV (115-300 nm VUV) and -radiation to investigate how these two forms of radiation affect the chemical, morphological, and piezoelectric properties of the polymers. The extent of crosslinking was almost identical in both polymers after -irradiation, but surprisingly, was significantly higher for the TrFE copolymer after VUV-irradiation. Changes in the melting behavior were also more significant in the TrFE copolymer after VUV-irradiation due to both surface and bulk crosslinking, compared with only surface crosslinking for the PVDF films. The piezoelectric properties (measured using d33 piezoelectric coefficients and D-E hysteresis loops) were unchanged in the PVDF homopolymer, while the TrFE copolymer exhibited more narrow D-E loops after exposure to either - or VUV-radiation. The more severe damage to the TrFE copolymer in comparison with the PVDF homopolymer after VUV-irradiation is explained by different energy deposition characteristics. The short wavelength, highly energetic photons are undoubtedly absorbed in the surface layers of both polymers, and we propose that while the longer wavelength components of the VUV-radiation are absorbed by the bulk of the TrFE copolymer causing crosslinking, they are transmitted harmlessly in the PVDF homopolymer.