A role for diatom-like silicon transporters in calcifying coccolithophores.

Biomineralization by marine phytoplankton, such as the silicifying diatoms and calcifying coccolithophores, plays an important role in carbon and nutrient cycling in the oceans. Silicification and calcification are distinct cellular processes with no known common mechanisms. It is thought that coccolithophores are able to outcompete diatoms in Si-depleted waters, which can contribute to the formation of coccolithophore blooms. Here we show that an expanded family of diatom-like silicon transporters (SITs) are present in both silicifying and calcifying haptophyte phytoplankton, including some globally important coccolithophores. Si is required for calcification in these coccolithophores, indicating that Si uptake contributes to the very different forms of biomineralization in diatoms and coccolithophores. Significantly, SITs and the requirement for Si are absent from highly abundant bloom-forming coccolithophores, such as Emiliania huxleyi. These very different requirements for Si in coccolithophores are likely to have major influence on their competitive interactions with diatoms and other siliceous phytoplankton.

A role for diatom-like silicon transporters in calcifying coccolithophores.

Biomineralization by marine phytoplankton, such as the silicifying diatoms and calcifying coccolithophores, plays an important role in carbon and nutrient cycling in the oceans. Silicification and calcification are distinct cellular processes with no known common mechanisms. It is thought that coccolithophores are able to outcompete diatoms in Si-depleted waters, which can contribute to the formation of coccolithophore blooms. Here we show that an expanded family of diatom-like silicon transporters (SITs) are present in both silicifying and calcifying haptophyte phytoplankton, including some globally important coccolithophores. Si is required for calcification in these coccolithophores, indicating that Si uptake contributes to the very different forms of biomineralization in diatoms and coccolithophores. Significantly, SITs and the requirement for Si are absent from highly abundant bloom-forming coccolithophores, such as Emiliania huxleyi. These very different requirements for Si in coccolithophores are likely to have major influence on their competitive interactions with diatoms and other siliceous phytoplankton.

Self-healing of cracks during ductile regime machining of silicon: Insights from molecular dynamics simulation

During nanoindentation and ductile-regime machining of silicon, a phenomenon known as “self-healing” takes place in that the microcracks, microfractures, and small spallings generated during the machining are filled by the plastically flowing ductile phase of silicon. However, this phenomenon has not been observed in simulation studies. In this work, using a long-range potential function, molecular dynamics simulation was used to provide an improved explanation of this mechanism. A unique phenomenon of brittle cracking was discovered, typically inclined at an angle of 45° to 55° to the cut surface, leading to the formation of periodic arrays of nanogrooves being filled by plastically flowing silicon during cutting. This observation is supported by the direct imaging. The simulated X-ray diffraction analysis proves that in contrast to experiments, Si-I to Si-II (beta tin) transformation during ductile-regime cutting is highly unlikely and solid-state amorphisation of silicon caused solely by the machining stress rather than the cutting temperature is the key to its brittle-ductile transition observed during the MD simulations

High-Performance WSe2 CMOS Technology and Integrated Circuits.

Because of their extraordinary structural and electrical properties, two dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (~38) and small static power (Pico-Watts), paving the way for low power electronic system in 2D materials.

Baker Program's Inaugural Domestic Trip to San Francisco and Silicon Valley

[Excerpt] In late January, first-year students in the Baker Program in Real Estate attended the first annual domestic real estate trek as part of the program’s newly revised curriculum. For this inaugural trip, students visited San Francisco and Silicon Valley, two of the nation’s most active real estate markets.

Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS

Résumé : Le transistor monoélectronique (SET) est un dispositif nanoélectronique très attractif à cause de son ultra-basse consommation d’énergie et sa forte densité d’intégration, mais il n’a pas les capacités suffisantes pour pouvoir remplacer complètement la technologie CMOS. Cependant, la combinaison de la technologie SET avec celle du CMOS est une voie intéressante puisqu’elle permet de profiter des forces de chacune, afin d’obtenir des circuits avec des fonctionnalités additionnelles et uniques. Cette thèse porte sur l’intégration 3D monolithique de nanodispositifs dans le back-end-of-line (BEOL) d’une puce CMOS. Cette approche permet d’obtenir des circuits hybrides et de donner une valeur ajoutée aux puces CMOS actuelles sans altérer le procédé de fabrication du niveau des transistors MOS. L’étude se base sur le procédé nanodamascène classique développé à l’UdeS qui a permis la fabrication de dispositifs nanoélectroniques sur un substrat de SiO2. Ce document présente les travaux réalisés sur l’optimisation du procédé de fabrication nanodamascène, afin de le rendre compatible avec le BEOL de circuits CMOS. Des procédés de gravure plasma adaptés à la fabrication de nanostructures métalliques et diélectriques sont ainsi développés. Le nouveau procédé nanodamascène inverse a permis de fabriquer des jonctions MIM et des SET métalliques sur une couche de SiO2. Les caractérisations électriques de MIM et de SET formés avec des jonctions TiN/Al2O3 ont permis de démontrer la présence de pièges dans les jonctions et la fonctionnalité d’un SET à basse température (1,5 K). Le transfert de ce procédé sur CMOS et le procédé d’interconnexions verticales sont aussi développés par la suite. Finalement, un circuit 3D composé d’un nanofil de titane connecté verticalement à un transistor MOS est réalisé et caractérisé avec succès. Les résultats obtenus lors de cette thèse permettent de valider la possibilité de co-intégrer verticalement des dispositifs nanoélectroniques avec une technologie CMOS, en utilisant un procédé de fabrication compatible.

Investigating routes toward atomic layer deposition of silicon carbide: Ab initio screening of potential silicon and carbon precursors

Silicon carbide (SiC) is a promising material for electronics due to its hardness, and ability to carry high currents and high operating temperature. SiC films are currently deposited using chemical vapor deposition (CVD) at high temperatures 1500–1600 °C. However, there is a need to deposit SiC-based films on the surface of high aspect ratio features at low temperatures. One of the most precise thin film deposition techniques on high-aspect-ratio surfaces that operates at low temperatures is atomic layer deposition (ALD). However, there are currently no known methods for ALD of SiC. Herein, the authors present a first-principles thermodynamic analysis so as to screen different precursor combinations for SiC thin films. The authors do this by calculating the Gibbs energy ΔGΔG of the reaction using density functional theory and including the effects of pressure and temperature. This theoretical model was validated for existing chemical reactions in CVD of SiC at 1000 °C. The precursors disilane (Si2H6), silane (SiH4), or monochlorosilane (SiH3Cl) with ethyne (C2H2), carbontetrachloride (CCl4), or trichloromethane (CHCl3) were predicted to be the most promising for ALD of SiC at 400 °C.

Silicon Promotes Exodermal Casparian Band Formation in Si-Accumulating and Si-Excluding Species by Forming Phenol Complexes

We studied the effect of Silicon (Si) on Casparian band (CB) development, chemical composition of the exodermal CB and Si deposition across the root in the Si accumulators rice and maize and the Si non-accumulator onion. Plants were cultivated in nutrient solution with and without Si supply. The CB development was determined in stained root cross-sections. The outer part of the roots containing the exodermis was isolated after enzymatic treatment. The exodermal suberin was transesterified with MeOH/BF3 and the chemical composition was measured using gas chromatography-mass spectroscopy (GC-MS) and flame ionization detector (GC-FID). Laser ablation-inductively coupled plasma-mass spectroscopy (LA-ICP-MS) was used to determine the Si deposition across root cross sections. Si promoted CB formation in the roots of Si-accumulator and Si non-accumulator species. The exodermal suberin was decreased in rice and maize due to decreased amounts of aromatic suberin fractions. Si did not affect the concentration of lignin and lignin-like polymers in the outer part of rice, maize and onion roots. The highest Si depositions were found in the tissues containing CB. These data along with literature were used to suggest a mechanism how Si promotes the CB development by forming complexes with phenols.

Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.

An 8x8 thermopile based uncooled infrared sensor

International audience