Defining a Research Agenda in Value Driven Design: Questions That Need to be Asked

Value driven design is an innovative design process that utilizes the optimization of a system level value function to determine the best possible design. This contrasts with more traditional systems engineering techniques, which rely on satisfying requirements to determine the design solution. While ‘design for value’ is intuitively acceptable, the transformation of value driven design concepts into practical tools and methods for its application is challenging. This, coupled with the growing popularity of value-centric design philosophies, has led to a proposed research agenda in value driven design. This research agenda asks fundamental questions about the design philosophy and attempts to identify areas of significant challenge. The research agenda is meant to stimulate discussion in the field, as well as prompt research that will lead to the development of tools and methodologies that will facilitate the application of value driven design and further the state of the art.

Transmit and receive filter design for OFDM based WLAN systems

We analyze the effect of different pulse shaping filters on the orthogonal frequency division multiplexing (OFDM) based wireless local area network (LAN) systems in this paper. In particular, the performances of the square root raised cosine (RRC) pulses with different rolloff factors are evaluated and compared. This work provides some guidances on how to choose RRC pulses in practical WLAN systems, e.g., the selection of rolloff factor, truncation length, oversampling rate, quantization levels, etc.

Voltage over-scaling:A cross-layer design perspective for energy efficient systems

Today's multi-media electronic era is driven by the increasing demand for small multifunctional devices able to support diverse services. Unfortunately, the high levels of transistor integration and performance required by such devices lead to an unprecedented increase of on-chip power that significantly limits the battery lifetime and even poses reliability concerns. Several techniques have been developed to address the power increase, but voltage over-scaling (VOS) is considered to be one of the most effective ones due to the quadratic dependence of voltage on dynamic power consumption. However, VOS may not always be applicable since it increases the delay in all paths of a system and may limit high performance required by today's complex applications. In addition, application of VOS is further complicated since it increases the variations in transistor characteristics imposed by their tiny size which can lead to large delay and leakage variations, making it difficult to meet delay and power budgets. This paper presents a review of various cross-layer design options that can provide solutions for dynamic voltage over-scaling and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems. © 2011 IEEE.

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of today's systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs ( logic, memory, mixed-signal) that are included in today's complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems.

Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.